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RISS 인기검색어
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- 저자 : Srini, Vason P. (검색결과 6 건)
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Srini R,Srinivasan,Sandeep Bhanot,Eun Jin Hwang 한국유통과학회 2017 한국유통과학회 학술대회 논문집 Vol.2017 No.-
The purpose of the study is to understand the influence of social value on the purchase of luxury brands to find whether the perception of social value differs with demographic variables like gender, occupation, age, income, education, religion and marital status. Data collected from 1200 respondents in Mumbai. It was found that social value has a significant effect on the purchase of luxury brands and there was a significant difference in perception of prestige value among people of different age groups, gender, occupation, religion, and monthly income. There was a significant difference in perception of snob value among people of various age groups, ethnicity, gender, and religions. Luxury brand companies can target the right target segment by understanding how social value influences the purchase of luxury brands and whether there is any significant difference in social value concerning the various demographic variables. They can devise strategies to enable the right target segment to access their products efficiently.
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Power and Knowledge: International Relations Scholarship in the Core and Periphery
( Srini Sitaraman ) 서울대학교 통일평화연구원 2016 Asian Journal of Peacebuilding Vol.4 No.2
The field of International Relations (IR) is motivated as much by the institutional dynamics of American universities and the internal rewards structure of tenure, promotion, and merit pay, as it is by wider scholarly recognition. This article discusses how the incentives of the U.S. academe influence IR theory and how it imitates the preferences of American foreign policy. Moreover, this article denotes that IR scholarship has abstracted away from the realities of international affairs and it does not speak of, or speak to those in the far away periphery. It concludes by discussing two promising movements: Global IR and Planet Politics. Global IR involves rebuilding the theories of IR by incorporating contributions from the periphery, whereas Planet Politics is a manifesto for rewriting IR as a set of practices based on the concept of Anthropocene by proposing a new ontology that is driven by the dread of planetary extinction.
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실시간 Dense Disparity Map 추출을 위한 고성능 가속기 구조 설계
김정길,Vason P. Srini,김신덕 한국정보처리학회 2007 정보처리학회논문지. 컴퓨터 및 통신시스템 Vol.14 No.5
This paper proposes high performance coprocessor architecture for realtime dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation (LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD (Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate. 본 논문에서는 위상기반 양안스테레오정합 알고리즘을 이용, 실시간으로 dense disparity map을 추출 가능한 고성능 가속기 구조를 설계하였다. 채택된 알고리즘은 웨이블릿 기반의 위상차 기법의 강건성과 위상상관 기법의 기본적인 control 기법을 결합한 Local Weighted Phase Correlation(LWPC) 스테레오정합 알고리즘으로서 4개의 주요 단계로 구성이 되어 있다. 해당 알고리즘의 효율적인 병렬 하드웨어의 설계를 위하여, 제안된 가속기는 각 단계의 기능블록은 SIMD(Single Instruction Multiple Data Stream) 모드로 동작하게 되며, 전체적으로 각 기능 블록은 파이프라인(pipeline) 모드로 실행된다. 그 결과 제안된 구조에서 제시된 파이프라인 동작 모드의 선형 배열 프로세서는 행렬 순차수행 방법에 의한 2차원 영상처리에서 전치메모리의 필요를 제거하면서도 연산의 일반성과 고효율을 유지하게 한다. 제안된 하드웨어 구조는 Xilinx HDL을 이용하여 필요한 하드웨어 자원을 look up table, flip flop, slice, memory의 소모량으로 표현하였으며, 그 결과 실시간 처리 성능의 단일 칩 구현 가능성을 보여주었다.
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High Performance Coprocessor Architecture for Real-Time Dense Disparity Map
김정길,김신덕,Kim, Cheong-Ghil,Srini, Vason P.,Kim, Shin-Dug Korea Information Processing Society 2007 정보처리학회논문지 A Vol.14 No.5
본 논문에서는 위상기반 양안스테레오정합 알고리즘을 이용, 실시간으로 dense disparity map을 추출 가능한 고성능 가속기 구조를 설계하였다. 채택된 알고리즘은 웨이블릿 기반의 위상차 기법의 강건성과 위상상관 기법의 기본적인 control 기법을 결합한 Local Weighted Phase Correlation(LWPC) 스테레오정합 알고리즘으로서 4개의 주요 단계로 구성이 되어 있다. 해당 알고리즘의 효율적인 병렬 하드웨어의 설계를 위하여, 제안된 가속기는 각 단계의 기능블록은 SIMD(Single Instruction Multiple Data Stream) 모드로 동작하게 되며, 전체적으로 각 기능 블록은 파이프라인(pipeline) 모드로 실행된다. 그 결과 제안된 구조에서 제시된 파이프라인 동작 모드의 선형 배열 프로세서는 행렬 순차수행 방법에 의한 2차원 영상처리에서 전치메모리의 필요를 제거하면서도 연산의 일반성과 고효율을 유지하게 한다. 제안된 하드웨어 구조는 Xilinx HDL을 이용하여 필요한 하드웨어 자원을 look up table, flip flop, slice, memory의 소모량으로 표현하였으며, 그 결과 실시간 처리 성능의 단일 칩 구현 가능성을 보여주었다. This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.
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Designing a Generic Compiler for Scalable Computing Fabric
타로파 에마뉴엘(Emanuel Taropa),이원종(Won-Jong Lee),바슨 스리니(Vason P. Srini),한탁돈(Tack-Don Han) 한국정보과학회 2006 한국정보과학회 학술발표논문집 Vol.33 No.1
A blooming area of processor design is represented by scalable computing fabric. As the structure of the processors developed using scalable computing fabric evolved from simple programmable units to processors supporting change of flow instructions and function calls. an increasing interest is in developing the compiling technology that will allow us to harness not only the full power of their hardware but also to target multiple architectures. In this paper we present the front-end of a generic compiler, able to accept a various source languages and transform them in a common intermediate representation.
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후정렬 병렬 가시화 클러스터를 위한 저비용의 하드웨어 영상 합성기
타로파 에마뉴엘(Emanuel Taropa),이원종(Won-Jong Lee),바슨 스리니(Vason P. Srini),한탁돈(Tack-Don Han) 한국정보과학회 2005 한국정보과학회 학술발표논문집 Vol.32 No.1
Real-time 3D visualization of large datasets imposes a distributed architecture of the rendering system and dedicated hardware for image composition. Previous work on this domain has relied on prohibitively expensive cluster systems with hardware composition done by complicated schemes. In this paper we propose a low-cost hardware compositor for a high performance visualization cluster. We show the system’s design and the results obtained using Simulink [1] for our image composition scheme.
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