Sensitive Vector Search for Logic Circuit Failure Probability based on Improved Adaptive Cuckoo Algorithm

Shuo Cai,Sicheng Wu,Weizheng Wang,Fei Yu,Lairong Yin 대한전자공학회 2022 Journal of semiconductor technology and science Vol.22 No.2

With the development of microelectronics technology, the feature size of integrated circuit continues to shrink, and circuit performance has been improved. At the same time, however, factors such as process disturbance, power noise, and particle radiation are having an increasingly serious influence on the Failure Probability of Circuits (FPC). Searching the input vectors that are sensitive to FPC can assist circuit designers in selectively reinforcing the circuit to reduce the fault-tolerant overhead and improve the fault-tolerant efficiency. In this paper, an Improved Adaptive Cuckoo Search (IACS) algorithm is proposed to search sensitive circuit vectors. The vector segmentation strategy is used to change the dimension of the input vector, the hill climbing algorithm is used to improve the quality of the initial population, and the adaptive strategy is used to control parameters such as power-law index, discovery probability and scaling factor. At the same time, a Correlation Separation Approach (COSEA) is proposed to calculate the FPC under specific vector excitation. Experimental results show that the proposed algorithm has higher accuracy and better efficiency compared with existing algorithms.

Soft Error Susceptibility Analysis for Sequential Circuit Elements Based on EPPM

CAI Shuo,KUANG Ji-shun,LIU Tie-qiao,WANG Wei-zheng 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.2

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS’89 benchmark circuits show that our method is more accurate and efficient than previous methods.

Grey fuzzy PI control for packing pressure during injection molding process

Shuo Wang,Ji Ying,Zichen Chen,Kan Cai 대한기계학회 2011 JOURNAL OF MECHANICAL SCIENCE AND TECHNOLOGY Vol.25 No.4

This study presents a grey fuzzy PI (GFPI) controller for packing pressure control during the injection process. The novel controller was designed for solving the problems of large overshoot, static error, and long delay time on servo motor-driven injection molding machines. Based on reasonable assumptions, a mathematical model of injection system was established. According to the nonlinear, severe interferences, and long delay time characteristics in injection process, this paper integrates predictive grey system, robust fuzzy ratiocination,and PI control. Using these mathematical model and control algorithms, a GFPI controller is implemented into an MCU using C programming techniques. The integral discrete PID controller and solid fuzzy controller were realized for contrast experiments. The experimental results show that GFPI controller had better performance on reducing overshoot and static error, increasing both response rate and repeatable accuracy. Such a developed technology would provide helpful references for designing the controller of energy-saving servo motor-driven injection molding equipment.

Reducing Test Power and Improving Test Effectiveness for Logic BIST

Wang Weizheng,Cai Shuo,Xiang Lingyun 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.5

Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS’89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

SOC Test Compression Scheme Sharing Free Variables in Embedded Deterministic Test Environment

Wang Weizheng,Cai Shuo,Xiang Lingyun 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.3

This paper presents a new SOC test compression scheme in Embedded Deterministic Test (EDT) compression environment. Compressed test data is brought over the TAM from the tester to the cores in SOC and decompressed in the cores. The proposed scheme allows cores tested at the same time to share some test channels. By sharing free variables in these channels across test cubes of different cores decompressed at the same time, high encoding efficiency is achieved. Moreover, no excess control data is required in this scheme. The ability to reuse excess free variables eliminates the need for high precision in matching the number of test channels with the number of care bits for every core. Experimental results obtained for some SOC designs illustrate effectiveness of the proposed test application scheme.

Compression-Friendly Low Power Test Application Based on Scan Slices Reusing

Wang Weizheng,Wang JinCheng,Cai Shuo,Su Wei,Xiang Lingyun 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.4

This paper presents a compression-friendly low power test scheme in EDT environment. The proposed approach exploits scan slices reusing to reduce the switching activity during shifting for test scheme based on linear decompressor. To avoid the impact on encoding efficiency from resulting control data, a counter is utilized to generate control signals. Experimental results obtained for some larger ISCAS’89 and ITC’99 benchmark circuits illustrate that the proposed test application scheme can improve significantly the encoding efficiency of linear decompressor.

Multi-RIS Aided 3D Secure Precise Wireless Transmission

Tong Shen,Wenlong Cai,Yan Lin,Shuo Zhang,Jinyong Lin,Feng Shu,Jiangzhou Wang 한국통신학회 2022 Journal of communications and networks Vol.24 No.5

In this paper, multiple reconfigurable intelligent surfaces (RIS) aided secure precise wireless transmission (SPWT) schemes are proposed in the three-dimensional (3D) wire- less communication scenario. Unavailable direct path channels from transmitter to receivers are considered when the di- rect paths are obstructed by obstacles. Then, multiple RISs are utilized to achieve SPWT through the reflection path among transmitter, RISs and receivers in order to enhance the communication performance and energy efficiency simulta- neously. First, a maximum-signal-to-interference-and-noise ratio (MSINR) scheme is proposed in a single user scenario. Then, the multi-user scenario is considered where the illegitimate users are regarded as eavesdroppers. A maximum-secrecy-rate (MSR) scheme and a maximum-signal-to-leakage-and-noise ratio (MSLNR) are proposed. The former achieves a better secrecy rate (SR) performance but incurs a higher complexity. The latter has a lower complexity than the MSR scheme with an SR performance loss. Simulation results show that both single- user scheme and multi-user scheme can achieve SPWT which transmits confidential message precisely to location of desired users. Moreover, MSLNR scheme has a lower complexity than the MSR scheme, while the SR performance is close to that of the MSR scheme.

Benzochloroporphyrin Derivative Induced Cytotoxicity and Inhibition of Tumor Recurrence During Photodynamic Therapy for Osteosarcoma

Gong, Hai-Yang,Sun, Meng-Xiong,Hu, Shuo,Tao, Ying-Ying,Gao, Bo,Li, Guo-Dong,Cai, Zheng-Dong,Yao, Jian-Zhong Asian Pacific Journal of Cancer Prevention 2013 Asian Pacific journal of cancer prevention Vol.14 No.5

Photodynamic therapy (PDT) is a promising cancer treatment modality that uses dye-sensitized photooxidation of biologic matter in target tissue. This study explored effects of the photosensitizer BCPD-17 during PDT for osteosarcoma. LM-8 osteosarcoma cells were treated with BCPD-17 and cell viability after laser irradiation was assessed in vitro with the 3-(4, 5-dimethylthiazol-2-yl)-2, 5-diphenyltetrazolium bromide assay. The effects of BCPD-17 during PDT recurrence were then examined on tumor-bearing mice in vivo. BCPD-17 had dosedependent cytotoxic effects on LM-8 osteosarcoma cells after laser irradiation which also had energy-dependent effects on the cells. The rate of local recurrence was reduced when marginal resection of mice tumors was followed by BCPD-17-mediated PDT. Our results indicated BCPD-17-mediated PDT in combination with marginal resection of tumors is a potentially new effective treatment for osteosarcoma.

Enhanced Biotransformation Productivity of Gamma-Decalactone from Ricinoleic Acid Based on the Expanded Vermiculite Delivery System

( Shimin Guan ),( Shaofeng Rong ),( Mengze Wang ),( Baoguo Cai ),( Qianqian Li ),( Shuo Zhang ) 한국미생물·생명공학회 2019 Journal of microbiology and biotechnology Vol.29 No.7

Natural gamma-decalactone (GDL) produced by biotransformation is an essential food additive with a peach-like aroma. However, the difficulty of effectively controlling the concentration of the substrate ricinoleic acid (RA) in water limits the biotransformation productivity, which is a bottleneck for industrialization. In this study, expanded vermiculite (E-V) was utilized as a carrier of RA to increase its distribution in the medium. E-V and three commonly used organic compounds were compared with respect to their effects on the biotransformation process, and the mechanism was revealed. Scanning electron microscopy, Fourier transform infrared spectroscopy and thermogravimetric analysis indicated that RA was physically adsorbed onto the surface of and inside E-V instead of undergoing a chemical reaction, which increased the opportunity for interactions between microorganisms and the substrate. The highest concentration of GDL obtained in the medium with E-V was 6.2 g/l, which was 50% higher than that in the reference sample. In addition, the presence of E-V had no negative effect on the viability of the microorganisms. This study provides a new method for producing natural GDL through biotransformation on an industrial scale.

A Secure Scan Design based on Scan Scrambling by Pseudorandom Values and Circuit Itself

Weizheng Wang,Yan Peng,Zuoting Ning,Peng Liu,Shuo Cai 대한전자공학회 2021 Journal of semiconductor technology and science Vol.21 No.6

Scan-based Design-for-Testability (DfT) methodology has been employed extensively in intellectual property (IP) design to guarantee the testing efficiency. Nevertheless, it also becomes a liability for IP core security because the adversary can steal sensitive information such as secret keys by scan-based attacks. Many protection strategies have been proposed to oppose the scan-based noninvasive attacks by obfuscating the test data. Regrettably, most of these strategies incur the IP performance degradation or put forward the unacceptable resource requirement. In this paper, we propose a new secure scan design scheme, which scramble the test patterns with pseudo-random values and the test responses with selected internal nodes of the circuit. Without the knowledge of circuit design, the adversary cannot apply desired test patterns and cannot recover factual test responses. Thus, it can be prevented to deduce the sensitive information by scan attacks. Through simulation experiments and theoretical analyses, the proposed approach can guarantee the chip security with very low overhead and no impact on the testability.