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      • SCISCIESCOPUS

        Microstructural stability of SSC fibrous cathode with embedded SDC particles for solid oxide fuel cells operating on hydrogen

        Lee, Sewook,Choi, Jinyi,Shin, Dongwook Elsevier 2018 International journal of hydrogen energy Vol.43 No.24

        <P><B>Abstract</B></P> <P>The research dealing with performance enhancement by Sm<SUB>0.5</SUB>Sr<SUB>0.5</SUB>CoO<SUB>3−δ</SUB> (SSC) fibrous cathode with embedded Sm<SUB>0.2</SUB>Ce<SUB>0.8</SUB>O<SUB>1.9</SUB> (SDC) particles has been reported by our previous study. In this paper, in order to assess the feasibility and reliability of this fibrous SSC-SDC cathode as a practical cathode, we conducted the short-term stability test using a half-cell under cathodic polarization treatment to identify the degradation phenomena only at the cathode. The polarization treatment was conducted under the current density of 500 mA/cm<SUP>2</SUP>. The stability test was carried out at 700 °C in air under the condition of open circuit. After the measurement, the resistance associated with charge transfer and surface catalytic reaction were increased by 159 and 77%, respectively. The reasons for this degradation can be considered common approaches of perovskites cathode materials such as grain growth and Sr-enrichment. Fortunately, the fibers maintain their original shape, porosity and interfacial adhesion to electrolyte.</P> <P><B>Highlights</B></P> <P> <UL> <LI> SSC fibrous cathode with embedded SDC particles. </LI> <LI> We conduct the short-term stability test under cathodic polarization. </LI> <LI> Reasons for degradation are considered both of grain growth and Sr-enrichment. </LI> <LI> Fibers retain their shape, porosity and interfacial adhesion after test. </LI> </UL> </P>

      • KCI등재
      • Memory Thin Film Transistor with Monolayered Nanoparticles through Chemical and Biological Bindings

        Lee, Hyun Ho,Jung, Hunsang,Kim, Minkeun,Kim, Yejin,Oh, Sewook,Yoon, Tae-Sik The Electrochemical Society 2013 ECS transactions Vol.50 No.8

        <P>To have an efficient monolayer of charging element in the memory OTFT, metallic or semiconductor nanoparticles (NPs) and surface of dielectric layers have been functionalized to accomplish specific binding mechanisms. In this study, using a strong chemical and biological binding system, polyaniline (PANI) NPs and Au NPs were monolayered between pentacene and organic dielectric layer in OTFT device. The PANI NPs were monolayered by epoxy-amine bonding and Au NPs were functionalized with streptavidin protein and the dielectric surface was modified by 3-amino-propyltriethoxysilane (APTES) and N-hydroxysuccinimide (NHS)-biotin. The memory OTFT can be applicable to develop a new conceptual device.</P>

      • SCISCIE

        A 1.62–5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques

        Sewook Hwang,Junyoung Song,Yeonho Lee,Chulwoo Kim IEEE 2017 IEEE Transactions on Circuits and Systems I: Regul Vol.64 No.10

        <P>We present a 1.62-5.4-Gb/s receiver for DisplayPort version 1.2a and propose an adaptive equalizer (EQ) with a peak-level comparison technique for eye measurement. A single comparator and an up/down unmatched-current charge pump are used to realize a simpler EQ architecture with low power dissipation. A referenceless frequency acquisition technique is also proposed. A time-to-digital converter-based pulsewidth detector supports the referenceless frequency acquisition within the range of 1.62-5.4 Gb/s. An XOR-gate-embedded charge pump and a half-rate linear phase detector were used to improve the jitter tolerance (JTOL) performance. The measured eye opening of the proposed EQ at 5.4 Gb/s was 0.68 UI with a -20-dB loss channel. The proposed receiver passed all the JTOL tests of the DisplayPort compliance specification version 1.2b. The power consumption of the receiver was 36.8 mW at 5.4 Gb/s. The receiver occupied a core area of 0.265 mm(2) using 65-nm CMOS process technology.</P>

      • A 0.008 <tex> ${\hbox {mm}}^{2}$</tex> 500 <tex> $\mu{\rm W}$</tex> 469 kS/s Frequency-to-Digital Converter Based CMOS Temperature Sensor With Process Variation Compensation

        Sewook Hwang,Jabeom Koo,Kisoo Kim,Hokyu Lee,Chulwoo Kim IEEE 2013 IEEE transactions on circuits and systems. a publi Vol.60 No.9

        <P>This paper presents a temperature sensor based on a frequency-to-digital converter with digitally controlled process compensation. The proposed temperature sensor utilizes ring oscillators to generate a temperature dependent frequency. The adjusted linear frequency difference slope is used to improve the linearity of the temperature sensor and to compensate for process variations. Furthermore, an additional process compensation scheme is proposed to enhance the accuracy under one point calibration. With one point calibration, the resolution of the temperature sensor is 0.18 <SUP>°</SUP>C/LSB and the maximum inaccuracy of 20 measured samples is less than ±1.5<SUP>°</SUP>C over a temperature range of 0<SUP>°</SUP>C ~ 110<SUP>°</SUP>C. The entire block occupies 0.008 mm<SUP>2</SUP> in 65 nm CMOS and consumes 500 μW at a conversion rate of 469 kS/s.</P>

      • An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers

        Sewook Hwang,Junyoung Song,Sang-Geun Bae,Yeonho Lee,Chulwoo Kim IEEE 2016 IEEE transactions on very large scale integration Vol.24 No.3

        <P>An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-of-band JTOL of 0.71 UIpp at 100 MHz with <10(-12) BER. This is 196% higher than a conventional receiver without the JTE. The source-synchronous receiver with the proposed JTE achieved 0.92 UIpp at 300 MHz with <10(-12) BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm(2) in a 0.13-mu m CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW.</P>

      • SCISCIESCOPUS

        12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces

        Lee, Yeonho,Choi, Yoonjae,Song, Junyoung,Hwang, Sewook,Bae, Sang-Geun,Jun, Jaehun,Kim, Chulwoo IEEE 2019 IEEE journal of solid-state circuits Vol.54 No.2

        <P>This paper presents a new pin/energy-efficient data and clock signaling scheme, named braid clock signaling (BCS). This signaling scheme efficiently embeds clock information into the data stream without data overhead, unnecessary pins, and channels for clock. To remove the data overhead, the clock information is embedded in every other data period. This high transition density (TD) leads to the enhanced jitter tracking performance of a receiver and increased stability. Furthermore, a spread transition scheme (STS) removes the additional power consumption for the embedded clock with little electromagnetic interference (EMI). As non-return-to-zero (NRZ) signaling uses only two voltage levels, the NRZ BCS secures a large input voltage margin at the receiver side, unlike other pin-efficient multi-level signaling schemes. An analysis of the secured voltage margin shows improved energy efficiency over conventional pin-efficient multi-level signaling schemes, even without consideration of their clocking power dissipation. The prototype transceiver is fabricated in a 28-nm CMOS process with a 12-Gb/s delay-locked loop (DLL)-based receiver over four lines.</P>

      • KCI등재

        친환경 임도포장공법 개발을 위한 기초연구

        오세욱(Sewook Oh),이길호(Gilho Lee),김동근(Donggeun Kim) 한국지반환경공학회 2013 한국지반환경공학회논문집 Vol.14 No.6

        본 논문에서는 친환경고화재와 자연토, 물을 혼합하여 포설한 후 다짐장비를 이용하여 지반을 고결시키는 임도포장공법에 대한 기초연구를 수행하였다. 포장체의 목표강도는 2.0MPa로 설정하였고 고화재의 혼합비, 자연토의 종류, 양생기간별로 공시체를 제작하여 일축압축강도특성과 내구성을 평가하였다. 일축압축강도시험은 동일한 혼합비의 시멘트를 혼합한 공시체와 친환경고화재를 혼합한 공시체를 제작하여 강도를 비교하였으며, 내구성 평가를 위한 시험은 표면마모시험, 유수저항성 시험 등을 수행하였다. 또한, 임도의 특성상 탐방객들도 이용이 가능하므로 보행만족도를 평가하기 위하여 쇠구슬과 골프공을 이용한 SB, GB시험을 수행 하였다. This study carried out fundamental study on the forest road pavement method of cementing the ground using the compaction equipment after laying by mixing with eco-friendly stabilizer, natural soil and water. Target strength of pavement was set to 2.0MPa and the specimen was produced per mixing ratio of cement, kinds of natural soil and curing period to evaluate the durability and unconfined compressive strength. Unconfined compressive strength test was conducted to compare strength by producing the test specimen mixing environment-friendly cement as well as the test specimen mixing cement with the same mixing ratio. To evaluate the durability, surface abrasion test and water flow resistance test were conducted. In addition, SB and GB tests were conducted using iron marble and golf ball to evaluate the walking satisfaction since it can be used by visitors due to the feature of forest road.

      • KCI등재

        삼축압축시험을 이용한 NSS 혼합토의 강도정수 평가

        오세욱(Sewook Oh),이길호(Gilho Lee),권혁기(Hyekkee Kwon),권영철(Youngcheul Kwon) 한국지반환경공학회 2013 한국지반환경공학회논문집 Vol.14 No.11

        흙 포장의 장점에도 불구하고 흙 자체의 성질을 개선하기 위한 고화재로 시멘트가 주로 사용되고 있는 점 등이 개선되지 않아 활발한 사용에 저해요인으로 지적되어 왔다. 최근 중금속 확산 등을 막고 소정의 강도를 확보할 수 있는 친환경 고화재가 개발되어 실제 적용되고 있다. 그러나 이러한 공법은 현장에서의 경험 등에 의해 배합을 결정하는 것이 현재까지의 상황이며, 좀더 체계적인 강도 파악에 대한 연구는 미흡한 실정이다. 따라서 본 연구에서는 혼합토에 대한 삼축압축시험을 혼합토의 혼합비율과 전단강도 특성의 상관성을 분석하기 위하여 실시하였다. 혼합토에 대한 삼축압축시험 결과로부터 준설점토와 모래, 그리고 화강풍화토와 유기질토의 네 가지의 흙 종류별로 점착력과 내부마찰각의 변화를 양생 기간에 따라 관찰하였다. 4가지의 연구 대상 지반중 준설점토와 화강풍화토의 점착력은 양생 기간이 늘어날수록 증가하는 추세를 뚜렷하게 보였다. 반면, 준설 모래와 유기질토는 양생 기간에 따른 증가가 적게 나타났으며, 점착력도 작았다. 내부마찰각의 경우에는 모든 원지반 재료에서 양생일수와 고화재의종류에 상관없이 일정한 경향을 나타냈다. Despite of the various merits of soil pavement, it has not been widely adapted because portland cement was conventionally used as soil stabilizer to improve the mechanical properties such strength parameters. Recently, natural soil stabilizer(NSS) were developed and virtually adopted to several case of soil pavement construction under control of heavy metal pollution compared to cement-used cases. However, the application of natural soil stabilizer is not settled yet, and empirical design have been widely adopted. In this study, therefore, the strength parameter of soil-NSS mixture was estimated by some triaxial compression tests, CU-test. From the tests, the relationship between curing period and strength parameter such as internal friction and effective cohesion was examined. As a result, effective cohesion of dredged clay and granite soil increased as curing time is increased. However, internal friction is almost same result in all soil type used in this study.

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