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Seongjae Cho,Il Han Park,Tae Hun Kim,Jung Hoon Lee,Jong Duk Lee,Hyungcheol Shin,Byung-Gook Park 대한전자공학회 2005 Journal of semiconductor technology and science Vol.5 No.3
Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2-D numerical simulation tool as the device simulator.
Acoustic Driving Simulator Design for Evaluating an In-car Speech Recognizer
Lee, Seongjae,Kang, Sunmee 한국음성학회 2013 말소리와 음성과학 Vol.5 No.2
This paper is on designing an indoor driving simulator to evaluate the performance of in-car speech recognizer when influenced by the elements, which lower the success rate of speech recognition. The proposed simulator simulates vehicle noise which was pre-recorded in diverse driving environments and driver’s speech. Additionally, the proposed Lombard effect conversion module in this simulator enables the speech recorded in a studio environment to convert into various possible driving scenarios. The relevant experimental results have confirmed that the proposed simulator is a feasible approach for realizing an effective method as it achieved similar speech recognition results to the real driving environment.
Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
LEE, Dong Seup,YANG, Hong-Seon,KANG, Kwon-Chil,LEE, Joung-Eob,LEE, Jung Han,CHO, Seongjae,PARK, Byung-Gook The Institute of Electronics, Information and Comm 2010 IEICE transactions on electronics Vol.93 No.5
<P>We propose a gate-all-around tunnel field effect transistor (GAA TFET) having a n-doped layer at the source junction and investigate its electrical characteristics with device simulation. By introducing the n-doped layer, band-to-band tunneling area is increased and tunneling barrier width is decreased. Also, electric field induced by gate bias is increased by the surrounding gate structure, which makes it possible to obtain a more abrupt band-bending. These effects bring about a significant improvement in on-current and subthreshold characteristics. GAA TFET with n-doped layer shows subthreshold swing at <I>I<SUB>d</SUB></I> =1nA/µm of 32.5mV/dec, average subthreshold swing of 20.6mV/dec. With comparison to other TFET structures, the merits of the proposed device are demonstrated and performance dependences on device parameters are characterized by extensive simulations.</P>
A Charge Trap Folded nand Flash Memory Device With Band-Gap-Engineered Storage Node
Seongjae Cho,Won Bo Shim,Yoon Kim,Jang-Gn Yun,Jong Duk Lee,Hyungcheol Shin,Jong-Ho Lee,Byung-Gook Park IEEE 2011 IEEE transactions on electron devices Vol.58 No.2
<P>A charge trap folded NAND (FNAND) Flash memory device with band-gap-engineered (BE) storage node is proposed. Because of the compact cell layout without junction contacts, a NAND Flash memory is the most suitable memory medium for electronic appliances. Two memory cells are put together to have a common vertical channel, which enables one to achieve a theoretical near-30-nm technology. The resulting array is made by folding the conventional 2-D Flash memory and is called FNAND. The memory storage node uses a BE stack structure, where the oxide-nitride-oxide multilayers replace the tunnel oxide. The fin structures for both wordline and bitline have been formed by sidewall spacer patterning, instead of photolithography. The fabrication processes for SONONOS NAND Flash memory having independent double gates are explained. Electrical characteristics regarding memory operations under paired cell interference are analyzed.</P>