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Functional Analysis of Novel Collectins
SeongJae Jang,Atsushi Fukuoh,Katsuki Ohtani,Kenichiro Mori,Itsuro Yoshida,Yasuhiko Suzuki,Nobutaka Wakamiya 한국당과학회 2010 한국당과학회 학술대회 Vol.2010 No.1
Collectins are a family of collagenous calcium-dependent defense lectins in animals. Their polypeptide chains consist of four regions: a cysteine-rich N-terminal domain, a collagen-like region, an alpha-helical coiled-coil neck domain and a C-terminal lectin or carbohydrate-recognition domain. These polypeptide chains form trimers that may assemble into larger oligomers. The best studied family members are the mannan-binding lectin, which is secreted into the blood by the liver, and the surfactant proteins A and D, which are secreted into the pulmonary alveolar and airway lining fluid. The collectins represent an important group of pattern recognition molecules, which bind to oligosaccharide structures and/or lipid moities on the surface of microorganisms. Collectin placenta 1 (CL-P1), a recently discovered scavenger receptor, mediates the uptake of oxidized low density lipoprotein and microbes. In this study, we investigated CL-P1-mediated binding and ingestion of yeast-derived zymosan bioparticles using Chinese hamster ovary (CHO) cells stably expressing human CL-P1 (CHO/CL-P1) and human vascular endothelial cells constitutively expressed CL-P1. The uptake of zymosan by CHO/CL-P1 was dependent upon the level of CL-P1 expressed on the membrane and was inhibited by cytochalasin D and wortmannin. The binding of zymosan was also inhibited by ligands of other scavenger receptors such as poly(I) and dextran sulfate. Real time reverse transcription-PCR analyses showed that other scavenger receptors, namely LOX-1, Stabilin-2, or macrophage receptor with collagenous structure (MARCO), were not expressed in human umbilical vein endothelial cells isolated from different individuals. Nonopsonic zymosan ingestion was inhibited in three primary cultured vascular endothelial cells, including different human umbilical vein endothelial cells from nine individuals treated with CL-P1 small interfering RNAs (siRNAs), although small interfering RNAs of other scavenger receptors had no effect on zymosan uptake in these cells. Furthermore, we confirmed that CL-P1 is expressed in human and murine vascular endothelial layers. Our results demonstrated that CL-P1 predominantly mediated phagocytosis for fungi in vascular endothelia.
Characterization of erbium-silicided Schottky diode junction
Jang, Moongyu,Kim, Yarkyeon,Shin, Jaeheon,Lee, Seongjae IEEE 2005 IEEE electron device letters Vol.26 No.6
Trap density, lifetime, and the Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted trap density, lifetime, and Schottky barrier height for hole are determined as 1.5×10<SUP>13</SUP> traps/cm<SUP>2</SUP>, 3.75 ms and 0.76 eV, respectively. By using the developed method, the interface of the Schottky diode can be evaluated quantitatively.
Characterization of 2-bit Recessed Channel Memory with Lifted Charge Trapping Node Scheme
Jang-Gn Yun,Il Han Park,Seongjae Cho,Jung Hoon Lee,Doo-Hyun Kim,Gil Sung Lee,Yoon Kim,Jong-Duk Lee,Byung-Gook Park 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
In this paper, characteristics of the 2-bit recessed channel memory with lifted charge storage nodes are investigated. The length between the charge storage nodes through channel, which is defined as the effective memory node length (Meff), is extended by lifting up them. The dependence of VTH window and short channel effect on the recessed depth is analyzed. Improvement of short channel effect is obtained because the recessed channel structure increases the effective channel length (Leff). This device shows highly scalable characteristics without suffering from the second bit effect.
A 2-Bit Recessed Channel Nonvolatile Memory Device With a Lifted Charge-Trapping Node
Jang-Gn Yun,Il Han Park,Seongjae Cho,Jung Hoon Lee,Doo-Hyun Kim,Gil Sung Lee,Yoon Kim,Jong Duk Lee,Byung-Gook Park IEEE 2009 IEEE TRANSACTIONS ON NANOTECHNOLOGY Vol.8 No.1
<P>A novel 2-bit recessed channel nonvolatile memory device is proposed in this paper. Physically separated two charge-trapping nodes are lifted up to achieve large sensing margin in highly scaled memory devices. A successful 2-bit/cell operation with effective suppression of second bit effect is achieved by adopting the lifted charge-trapping node scheme. In addition, the effect of the source/drain junction depth on memory operation characteristics is investigated.</P>
A Charge Trap Folded nand Flash Memory Device With Band-Gap-Engineered Storage Node
Seongjae Cho,Won Bo Shim,Yoon Kim,Jang-Gn Yun,Jong Duk Lee,Hyungcheol Shin,Jong-Ho Lee,Byung-Gook Park IEEE 2011 IEEE transactions on electron devices Vol.58 No.2
<P>A charge trap folded NAND (FNAND) Flash memory device with band-gap-engineered (BE) storage node is proposed. Because of the compact cell layout without junction contacts, a NAND Flash memory is the most suitable memory medium for electronic appliances. Two memory cells are put together to have a common vertical channel, which enables one to achieve a theoretical near-30-nm technology. The resulting array is made by folding the conventional 2-D Flash memory and is called FNAND. The memory storage node uses a BE stack structure, where the oxide-nitride-oxide multilayers replace the tunnel oxide. The fin structures for both wordline and bitline have been formed by sidewall spacer patterning, instead of photolithography. The fabrication processes for SONONOS NAND Flash memory having independent double gates are explained. Electrical characteristics regarding memory operations under paired cell interference are analyzed.</P>
CHO, Seongjae,LEE, Jung Hoon,KIM, Yoon,YUN, Jang-Gn,SHIN, Hyungcheol,PARK, Byung-Gook The Institute of Electronics, Information and Comm 2010 IEICE transactions on electronics Vol.93 No.5
<P>In performing the program operation of the NAND-type flash memory array, the program-inhibited cell is applied by a positive voltage at the gate, i.e., word-line (WL) on the floating channel while the program cell is applied by program voltage as the two ends, drain select line (DSL) and source select line (SSL), are turned on with grounded bit-line (BL). In this manner, the self-boosting of silicon channel to avoid unwanted program operation is made possible. As the flash memory device is aggressively scaled down and the channel doping concentration is increased accordingly, the coupling phenomena among WL, floating gate (FG)/storage node, and silicon channel, which are crucial factors in the self-boosting scheme, should be investigated more thoroughly. In this work, the dependences of self-boosting of channel potential on channel length and doping concentration in the 2-D conventional planar and 3-D FinFET NAND-type flash memory devices based on bulk-silicon are investigated by both 2-D and 3-D numerical device simulations. Since there hardly exists realistic ways of measuring the channel potential by physical probing, the series of simulation works are believed to offer practical insights in the variation of channel potential inside a flash memory device.</P>
신뢰성 있는 동작을 위한 수직 구조 플래시 메모리의 공정 및 전압 조건의 최적화 연구
조성재(Seongjae Cho),박일한(Il Han Park),이정훈(Jung Hoon Lee),윤장근(Jang-Gn Yun),김두현(Doo-Hyun Kim),이길성(Gil Sung Lee),김윤(Yun Kim),이동화(Dong Hua Li),신형철(Hyungcheol Shin),이종덕(Jong Duk Lee),박병국(Byung-Gook Park) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
Various efforts have been devoted to maximizing memory array densities nowadays. It cannot be overestimated that developments in both novel structures and process engineering should be accomplished to heighten the density. In this study, a novel structure in three-dimension is introduced Furthermore, we investigated the paired cell interference (PCI) which inevitably occurs in the read operation for this kind of 3-D memory devices Ways of establishing the read operation bias schemes for reliable operation are also examined.
Moongyu Jang,Yarkyeon Kim,Jaeheon Shin,Seongjae Lee,Kyoungwan Park 대한전자공학회 2004 Journal of semiconductor technology and science Vol.4 No.2
Silicided 50-nm-gate-length n-type Schottky barrier metal-oxide-semiconductor field-effect-transistors (SB-MOSFETs) with 5 nm gate oxide thickness are manufactured. The saturation current is 120 uA/uM and on/off-current ratio is higher than 10^5 with low leakage current less than 10nA/um. Novel phenomena of this device are discussed. The increase of tunneling current with the increase of drain voltage is explained using drain induced Schottky barrier thickness thinning effect. The abnormal increase of drain current with the decrease of gate voltage is explained by hole carrier injection from drain into channel. The mechanism of threshold voltage increase in SB-MOSFETs is discussed. Based on the extracted model parameters, the performance of 10-nm-gate-length that the subthreshold swing valve can be lower than 60mV/decade.