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Low-Power 12-bit 160-MS/s Pipeline A/D Converters
Mai Nozawa,Daisuke Kurose,Takeshi Ueno,Tetsuro Itakura 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
Low-power 12-bit 160-MS/s pipeline A/D converters are designed for wireless receivers. Instead of using ultra-deep submicron devices of low supply voltage, we employ analog-option devices that operate at supply voltage of 2.5V in a 90-㎚ CMOS process. To achieve lower power dissipation, an I/Q amplifier sharing technique is employed. Furthermore, charge transfer level shifters are proposed in S/H circuits and MDACs for realizing class-AB operation. The area is 1.1㎟, the simulated power dissipation is 75㎽/channel and the simulated ENOB is 11.15bit.