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RISS 인기검색어
- 검색키워드
- 저자 : Hossam Hassan (검색결과 5 건)
- 무료
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- 유료
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Power-Gating Sub-Threshold Source-Coupled Logic (PG-STSCL) circuits for ultra-low-power applications
Hassan, Hossam,Ibrahim, Sameh,Kim, HyungWon Elsevier 2018 Microelectronics Journal Vol.74 No.-
<P>The sub-threshold circuit design is regarded as a promising technique to provide considerable power reduction for ultra-low-power applications under tight energy constraints. This paper presents Power-Gating Sub-Threshold Source-Coupled Logic (PG-STSCL), which employs the fine-grain power gating at the gate level. It introduces isolation and retention circuits to ensure reliable propagation of data along a pipeline of power gated circuits, called a micro-pipeline. While the conventional STSCL circuits can considerably cut down the active power consumption, they have the drawback of continuous static current flow. To overcome this drawback, the proposed architecture shuts off the static current by utilizing the fine-grain power-gating technique. We have designed a 32-bit adder based on the proposed PG-STSCL gates in a 65 nm CMOS technology. The adder was simulated and compared to reference adders using standard CMOS gates, and conventional STSCL gates. Simulations demonstrated that the proposed gates provide a power reduction of 89.56% and 99.78% when compared to the standard CMOS and STSCL gates, respectively.</P>
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Design of Verilog-HDL Based Simulator for Network on Chips
Hossam Hassan,HyungWon Kim 대한전자공학회 2016 대한전자공학회 학술대회 Vol.2016 No.6
Network on Chips (NoCs) are proposed to solve communication bandwidth limitation in modern Multi-Processors System on Chip (MPSoC) systems. Researchers (prove) relies their proposed ideas using modeling and simulation to evaluate the performance of their novel ideas. In this paper, we present a Verilog-HDL based simulator for NoCs. It considered as a cycle-accurate simulator to simulate the real environment of NoCs. It has a set of parameters that can be modify for a determined test. Also, it has the capability to add and remove any of network or router components.
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Dual Mode CMOS Capacitive Fingerprint Sensor Array Readout Circuit
Hossam Hassan,HyungWon Kim(김형원) 대한전자공학회 2018 대한전자공학회 학술대회 Vol.2018 No.6
In this paper we introduce a CMOS capacitive Fingerprint with dual-mode and charge detection readout circuit embedded in each cell pixel. The readout circuit has two modes of operation and can work with/without analog-to-digital converter (ADC). The first mode utilize in-cell pixel comparator to give the final decision (Ridge -> 1 or Valley -> 0). However, the second mode utilize a programmable gain amplifier (PGA) to interface with the ADC.
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Peter Nyanor,Omayma El‑Kady,Hossam M. Yehia,Atef S. Hamada,Koichi Nakamura,Mohsen A. Hassan 대한금속·재료학회 2021 METALS AND MATERIALS International Vol.27 No.5
Aluminum matrix composites reinforced with reduced graphene oxide (rGO) and hybrid of carbon nanotube (CNT) andrGO are fabricated by solution coating powder metallurgy process. The hardness, wear resistance and coefficient of thermalexpansion (CTE) of the reinforced aluminum composites and the associated microstructural changes with rGO range(0.2–0.6 wt%) and hybrids of 0.2 wt% CNT–rGO at different ratios have been investigated. The intensive microstructuralobservations show that rGO is adsorbed on Al particles and uniformly distributed in the Al matrix composites. The hardnessvalues of the composites increase significantly with rGO reinforcement exhibiting the maximum hardness at 0.4 wt% rGO.Compared with the hybrid composites CNT–rGO/Al counterparts fabricated by the same route and wt. percent of 0.2, thehardness values in the hybrid CNT–rGO increase considerably. Similar to the hardness, the results of wear tests also exhibitcorresponding variation in the values of the wear rates. The improvement in the wear resistance of the hybrid CNT–rGO /Alcomposite is pronounced in this work. Whereas the rGO reinforcements decrease significantly the wear rate of the aluminumbaseby 98%, the wear resistance of the corresponding hybrid CNT–rGO is significantly higher than that of the precedingcomposites. Maximum CTE reduction of 28% was recorded for hybrid CNT–rGO (1:1) reinforced composite.
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Peter Nyanor,Omayma El‑Kady,Hossam M. Yehia,Atef S. Hamada,Mohsen A. Hassan 대한금속·재료학회 2021 METALS AND MATERIALS International Vol.27 No.4
Aluminium (Al) matrix reinforced with carbon nanotubes (CNT), micron-sized titanium carbide (TiC) particles, and bimodal(nano + micron) hybrid TiC–CNT is fabricated by solution ball milling, followed by cold compaction and vacuum sinteringto improve the mechanical properties and reduce thermal expansion. The hardness, wear resistance, compressive strength andCTE of pure Al, 0.6 wt% CNT/Al, 10 wt% TiC/Al, and hybrid 10–0.6 wt% TiC–CNT/Al composites have been investigated inthis work. Analysis of strengthening mechanisms based on theoretical models, microstructure, and properties of constituentmaterials is performed. Microstructure analysis reveals an excellent distribution of the reinforcement phase and no new phaseformation in sintered composites. The hardness value of bimodal TiC–CNT reinforced Al composite is significantly higherthan monomodal TiC reinforced composite, reaching 2.3 times the hardness value of pure Al. Similarly, the wear resistanceimproved, and CTE reduced with CNT and TiC addition but is even significantly better in the hybrid reinforced composite. Experimental values of CTE show good agreement with the theoretical model. The strength and ductility of materials aremutually exclusive, but the compressive strength of pure Al has been doubled without significant loss in ductility throughthe use of bimodal-sized hybrid TiC–CNT reinforcement in this work.
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