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최석현,최중범,D. G. Hasko 한국물리학회 2014 새물리 Vol.64 No.7
We study the nanoscale channels formed by using electron-beam lithography with an ultrasonic-assisted development (UAD). In contrast with the traditional method, the ultrasonic source and the introduction of a phenomenological method with a non-solvent produce more efficient development by resist polymer interactions and micro-streaming effect, yielding a reduction in aggregation size and surface roughness. The resulting nanoscale multilines patterned by using the UAD show higher sensitivity and contrast than those patterned by using the MIBK:IPA method. We finally obtain Si nanochannels of 5.98 nm in width, which can contribute to study the mesoscopic physics of nanostructures and quantum devices. 초음파를 이용한 현상 (Ultrasonic-assisted development: UAD) 을 도입한 전자빔 리소그래피를 사용하여 나노스케일 미세패터닝을 연구하였다. 기존의 MIBK:IPA 현상액을 이용하는 공정과는 대조적으로, 초음파와 비 용매의 사용은 보다 효율적인 현상 과정을 보였는데 이는 감광막 고분자의 상호작용 및 연속적인 마이크로 스트림밍 효과에 기인하며 결과적으로 응집 크기와 표면 거칠기에 현저한 감소를 보였다. 이러한 초음파 이용 현상 도입을 통해 얻은 나노스케일의 다중 채널 패터닝은 기존의 MIBK:IPA 방법에 비해 높은 민감도 및 대비도를 보였다. 최종적으로 5.98 nm 선폭의 미세 나노선을 얻었는데 이는 나노 구조 및 양자 소자의 중시 물리 현상 규명에 기여할 수 있을 것이다.
Nedelcu, Mihaela,Saifullah, Mohammad S. M.,Hasko, David G.,Jang, Arang,Anderson, David,Huck, Wilhelm T. S.,Jones, Geraint A. C.,Welland, Mark E.,Kang, Dae Joon,Steiner, Ullrich WILEY-VCH Verlag 2010 Advanced Functional Materials Vol.20 No.14
<P>The fabrication of very narrow metal lines by the lift-off technique, especially below sub-10 nm, is challenging due to thinner resist requirements in order to achieve the lithographic resolution. At such small length scales, when the grain size becomes comparable with the line-width, the built-in stress in the metal film can cause a break to occur at a grain boundary. Moreover, the line-width roughness (LWR) from the patterned resist can result in deposited metal lines with a very high LWR, leading to an adverse change in device characteristics. Here a new approach that is not based on the lift-off technique but rather on low temperature hydrogen reduction of electron-beam patterned metal naphthenates is demonstrated. This not only enables the fabrication of sub-10 nm metal lines of good integrity, but also of low LWR, below the limit of 3.2 nm discussed in the International Technology Roadmap for Semiconductors. Using this method, sub-10 nm nickel wires are obtained by reducing patterned nickel naphthenate lines in a hydrogen-rich atmosphere at 500 °C for 1 h. The LWR (i.e., 3 σ<SUB>LWR</SUB>) of these nickel nanolines was found to be 2.9 nm. The technique is general and is likely to be suitable for fabrication of nanostructures of most commonly used metals (and their alloys), such as iron, cobalt, nickel, copper, tungsten, molybdenum, and so on, from their respective metal–organic compounds.</P> <B>Graphic Abstract</B> <P>Sub-10 nm nickel wires of good integrity are obtained by reducing electron-beam-patterned nickel naphthenate lines in a hydrogen-rich atmosphere at 500 °C for 1 h. The line-width roughness (i.e., 3 σ<SUB>LWR</SUB>) of these nickel nanolines is found to be 2.9 nm, which is below the limit of 3.2 nm discussed in the International Technology Roadmap for Semiconductors. <img src='wiley_img_2010/1616301X-2010-20-14-ADFM201000219-content.gif' alt='wiley_img_2010/1616301X-2010-20-14-ADFM201000219-content'> </P>
Nedelcu, Mihaela,Saifullah, Mohammad S. M.,Hasko, David G.,Jang, Arang,Anderson, David,Huck, Wilhelm T. S.,Jones, Geraint A. C.,Welland, Mark E.,Kang, Dae Joon,Steiner, Ullrich WILEY-VCH Verlag 2010 Advanced Functional Materials Vol.20 No.14
<B>Graphic Abstract</B> <P>This computer rendered graphic displays direct writing of sub-10 nm metallic wires of low line-width roughness using an electron beam (shown as a sinusoidal wave), as presented by M. S. M. Saifullah, D. J. Kang, U. Steiner, et al. on page 2317. Sub-10 nm metallic wires of good integrity and low line-width roughness were obtained by reducing electron-beam patterned metal naphthenate lines in a hydrogen-rich atmosphere at 500°C for 1 h. <img src='wiley_img_2010/1616301X-2010-20-14-ADFM201090059-content.gif' alt='wiley_img_2010/1616301X-2010-20-14-ADFM201090059-content'> </P>
Controllable Interdot Coupling in a Si-based Double Quantum Dot System for a Qubit Gate
J. J. Lee,J. S. Kim,S. J. Shin,J. B. Choi,D. G. Hasko 한국물리학회 2014 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.64 No.11
We have implemented a Si-based coupled double-dot device with five independent gates verticallylayered above the active channel, which can provide more effective controllability of interdot couplingwithout changing the potential shape of an individual dot. We observed a transition from a mergedsingle dot to the coupled double dot by adjusting the interdot coupling strength via a central gate. From the honeycomb charge stability diagram, the capacitance-related critical parameters of thecoupled double dot, which will be of impotance in the Si-based two-qubit gate applications, arededuced.
Room-Temperature Charge Stability Modulated by Quantum Effects in a Nanoscale Silicon Island
Shin, S. J.,Lee, J. J.,Kang, H. J.,Choi, J. B.,Yang, S.-R. Eric,Takahashi, Y.,Hasko, D. G. American Chemical Society 2011 Nano letters Vol.11 No.4
<P>We report on transport measurement performed on a room-temperature-operating ultrasmall Coulomb blockade devices with a silicon island of sub5 nm. The charge stability at 300K exhibits a substantial change in slopes and diagonal size of each successive Coulomb diamond, but remarkably its main feature persists even at low temperature down to 5.3K except for additional Coulomb peak splitting. This key feature of charge stability with additional fine structures of Coulomb peaks are successfully modeled by including the interplay between Coulomb interaction, valley splitting, and strong quantum confinement, which leads to several low-energy many-body excited states for each dot occupancy. These excited states become enhanced in the sub5 nm ultrasmall scale and persist even at 300K in the form of cluster, leading to the substantial modulation of charge stability.</P><P><B>Graphic Abstract</B> <IMG SRC='http://pubs.acs.org/appl/literatum/publisher/achs/journals/content/nalefd/2011/nalefd.2011.11.issue-4/nl1044692/production/images/medium/nl-2010-044692_0008.gif'></P>
Nanoscale memory cell based on a nanoelectromechanical switched capacitor
Jang, Jae Eun,Cha, Seung Nam,Choi, Young Jin,Kang, Dae Joon,Butler, Tim P.,Hasko, David G.,Jung, Jae Eun,Kim, Jong Min,Amaratunga, Gehan A. J. Springer Science and Business Media LLC 2008 Nature nanotechnology Vol.3 No.1
<P>The demand for increased information storage densities has pushed silicon technology to its limits and led to a focus on research on novel materials and device structures, such as magnetoresistive random access memory and carbon nanotube field-effect transistors, for ultra-large-scale integrated memory. Electromechanical devices are suitable for memory applications because of their excellent 'ON-OFF' ratios and fast switching characteristics, but they involve larger cells and more complex fabrication processes than silicon-based arrangements. Nanoelectromechanical devices based on carbon nanotubes have been reported previously, but it is still not possible to control the number and spatial location of nanotubes over large areas with the precision needed for the production of integrated circuits. Here we report a novel nanoelectromechanical switched capacitor structure based on vertically aligned multiwalled carbon nanotubes in which the mechanical movement of a nanotube relative to a carbon nanotube based capacitor defines 'ON' and 'OFF' states. The carbon nanotubes are grown with controlled dimensions at pre-defined locations on a silicon substrate in a process that could be made compatible with existing silicon technology, and the vertical orientation allows for a significant decrease in cell area over conventional devices. We have written data to the structure and it should be possible to read data with standard dynamic random access memory sensing circuitry. Simulations suggest that the use of high-k dielectrics in the capacitors will increase the capacitance to the levels needed for dynamic random access memory applications.</P>
Lee, Sungsik,Nathan, Arokia,Alexander-Webber, Jack,Braeuninger-Weimer, Philipp,Sagade, Abhay A.,Lu, Haichang,Hasko, David,Robertson, John,Hofmann, Stephan American Chemical Society 2018 ACS APPLIED MATERIALS & INTERFACES Vol.10 No.13
<P>A positive shift in the Dirac point in graphene field-effect transistors was observed with Hall-effect measurements coupled with Kelvin-probe measurements at room temperature. This shift can be explained by the asymmetrical behavior of the contact resistance by virtue of the electron injection barrier at the source contact. As an outcome, an intrinsic resistance is given to allow a retrieval of an intrinsic carrier mobility found to be decreased with increasing gate bias, suggesting the dominance of short-range scattering in a single-layer graphene field-effect transistor. These results analytically correlate the field-effect parameters with intrinsic graphene properties.</P> [FIG OMISSION]</BR>