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K-Nearest Neighbor Associative Memory with Reconfigurable Word-Parallel Architecture
Fengwei An,Keisuke Mihara,Shogo Yamasaki,Lei Chen,Hans Jurgen Mattausch 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.4
IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vector-component parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 ㎚ CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 ㎽ and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 ㎒ and 1.8 V).
K-Nearest Neighbor Associative Memory with Reconfigurable Word-Parallel Architecture
An, Fengwei,Mihara, Keisuke,Yamasaki, Shogo,Chen, Lei,Mattausch, Hans Jurgen The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.4
IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vector-component parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 nm CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 mW and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 MHz and 1.8 V).