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RISS 인기검색어
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- 저자 : Choi Seonil (검색결과 5 건)
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Kwon, Seonil,Kim, Hyuncheol,Choi, Seungyeop,Jeong, Eun Gyo,Kim, Dohong,Lee, Somin,Lee, Ho Seung,Seo, Young Cheol,Choi, Kyung Cheol American Chemical Society 2018 Nano letters Vol.18 No.1
<P>Fiber-based wearable displays, one of the most desirable requisites of electronic textiles (e-textiles), have emerged as a technology for their capability to revolutionize textile and fashion industries in collaboration with the state-of-the-art electronics. Nonetheless, challenges remain for the fibertronic approaches, because fiber-based light-emitting devices suffer from much lower performance than those fabricated on planar substrates. Here, we report weavable and highly efficient fiber-based organic light-emitting diodes (fiber OLEDs) based on a simple, cost-effective and low-temperature solution process. The values obtained for the fiber OLEDs, including efficiency and lifetime, are similar to that of conventional glass-based counterparts, which means that these state-of-the-art, highly efficient solution processed planar OLEDs can be applied to cylindrical shaped fibers without a reduction in performance. The fiber OLEDs withstand tensile strain up to 4.3% at a radius of 3.5 mm and are verified to be weavable into textiles and knitted clothes by hand-weaving demonstrations. Furthermore, to ensure the scalability of the proposed scheme fiber OLEDs with several diameters of 300, 220, 120, and 90 μm, thinner than a human hair, are demonstrated successfully. We believe that this approach, suitable for cost-effective reel-to-reel production, can realize low-cost commercially feasible fiber-based wearable displays in the future.</P> [FIG OMISSION]</BR>
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Yousang Yoon,Sunki Cho,Seonil Kim,Eunsuk Choi,Rae-Kwon Kim,Su-Jae Lee,Onejae Sul,Seung-Beck Lee IEEE Service Center 2014 Conference proceedings Vol.36 No.-
<P>We report on a microfluidic trap array that separates and captures circulating tumor cells (CTCs) from whole blood. The device is a series array of microfluidic branches that utilizes the difference in flow rates between the bypass channel and the trap channel to allow CTCs in whole blood to be separated and trapped. Once a trap has captured a cell with diameter larger than the narrow trap outlet, additional cells arriving at the branch would flow towards the bypass channel due to its lower flow resistance. Results demonstrated that it was possible to capture CTCs from the whole blood of a mouse with full-blown metastasis. With further developments, the bypass integrated microfluidic trap array could become a useful tool for the early prognosis of cancer metastasis.</P>
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A Review of Flexible OLEDs Toward Highly Durable Unusual Displays
Lee, Sung-Min,Kwon, Jeong Hyun,Kwon, Seonil,Choi, Kyung Cheol IEEE 2017 IEEE transactions on electron devices Vol.64 No.5
<P>Organic light-emitting diodes (OLEDs) are remarkably promising display devices that can function in mechanically flexible configurations on a plastic substrate due to various compelling properties, including organic constituents, ultrathin and simple structure, and low-temperature fabrication. In spite of successful demonstrations of flexible OLEDs, some technical issues of containing relatively thick transparent electrodes made of ceramic materials and an unstable flexible encapsulation system have impeded reaching high levels of reliability and durability toward full commercialization. This review covers recent developments in structure designs for highly durable flexible OLEDs, ranging from alternative transparent electrodes to thin-film encapsulation layers, in which solution concepts for the existing critical issues of flexible OLEDs are addressed. Emerging unusual substrates and their application strategies are additionally introduced to find intimations of future display technologies and hence to disclose nonclassic flexible OLEDs.</P>
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FPGA에서 에너지 효율이 높은 데이터 경로 구성을 위한 계층적 설계 방법
장주욱,이미숙,최선일,Jang Ju-Wook,Lee Mi-Sook,Mohanty Sumit,Choi Seonil,Prasanna Viktor K. 한국정보처리학회 2005 정보처리학회논문지 A Vol.12 No.5
본 논문은 ffGA상에서 에너지 효율이 높은 데이터 경로 설계 방법론을 제안한다. 에너지, 처리시간, 그리고 면적간의 트레이드오프를 이해하기 위하여, 도메인 특성 모델링, coarse-grained 성능평가, 설계공간 조사, 그리고 로우-레벨 시뮬레이션 과정들을 통합한다. 도메인 특성 모델링 기술은 도메인의 특성에 따른 시스템 전체의 에너지 모에 영향을 미치는 여러 가지 구성요소와 파라미터들을 식별함으로써 하이-레벨 모델을 명시한다. 도메인이란 주어진 어플리케이션 커널의 알고리즘에 대응하는 아키텍쳐 패밀리이다. 하이-레벨 모델 또한 에너지, 처리시간 그리고 면적을 예측하는 함수들로 구성되어 트레이드오프 분석을 용이하게 한다. 설계 공간 조사(DSE)는 도메인에 명시된 설계 공간을 분석하여 설계 셋을 선택하도록 한다. 로우-레벨 시뮬레이션은 설계 공간 조사(DSE)에 의해 선택된 설계와 최종 선택된 설계의 정확한 성능평가를 위하여 사용된다. 본 논문에서 제안한 설계 방법은 매트릭스 곱셈에 대응하는 알고리즘과 아키텍쳐 패밀리를 사용한다. 제안된 방법에 의해 검증된 설계는 에너지, 처리시간과 면적간의 트레이드오프를 보인다. 제안된 설계 방법의 효율성을 보이기 위하여 Xilinx에서 제공되는 매트릭스 곱셈 커널과 비교하였다. 성능 비교 메트릭으로 평균 전력 밀도(E/AT)와 에너지 대 (면적 x 처리시간)비를 사용하였다. 다양한 문제의 크기에 대하여 Xilinx설계들과 비교하였을 때 제안한 설계 방법이 전력밀도(E/AT)에서 평균 $25\%$우수하였다. 또한 본 논문에 제안한 설계의 방법을 MILAN 프레임워크를 이용하여 구현하였다. We present a methodology to design energy-efficient data paths using FPGAs. Our methodology integrates domain specific modeling, coarse-grained performance evaluation, design space exploration, and low-level simulation to understand the tradeoffs between energy, latency, and area. The domain specific modeling technique defines a high-level model by identifying various components and parameters specific to a domain that affect the system-wide energy dissipation. A domain is a family of architectures and corresponding algorithms for a given application kernel. The high-level model also consists of functions for estimating energy, latency, and area that facilitate tradeoff analysis. Design space exploration(DSE) analyzes the design space defined by the domain and selects a set of designs. Low-level simulations are used for accurate performance estimation for the designs selected by the DSE and also for final design selection We illustrate our methodology using a family of architectures and algorithms for matrix multiplication. The designs identified by our methodology demonstrate tradeoffs among energy, latency, and area. We compare our designs with a vendor specified matrix multiplication kernel to demonstrate the effectiveness of our methodology. To illustrate the effectiveness of our methodology, we used average power density(E/AT), energy/(area x latency), as themetric for comparison. For various problem sizes, designs obtained using our methodology are on average $25\%$ superior with respect to the E/AT performance metric, compared with the state-of-the-art designs by Xilinx. We also discuss the implementation of our methodology using the MILAN framework.
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