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RISS 인기검색어
- 검색키워드
- 저자 : Chang Keh-Jeng (검색결과 3 건)
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Physical and Technological Limitations and Their Optimizations in Submicron ULSI Interconnect
Oh, Soo Young,Chang, Keh JEng,Moll, John L. 대한전자공학회 1991 ICVC : International Conference on VLSI and CAD Vol.2 No.1
The trend of the performance degradations, noise and reliability issues and their potential solutions are analyzed for the submicron ULSI interconnect lines. Ta analyze these submicron interconnect lines, a new paradigm(HIVIE) for fast and accurate 2-D and 3-D interconnect capacitances and resistances calculation is developed. The analysis, using these interconnect parameters from HIVE, shows that a copper(Cu) line will improve the electromigrations, but not the interconnect delay and cross-talk noise significantly. The low temperature operation improve the interconnect delay and electromigration, but it increases the cost of system packaging. The optimum approach will be the combination of additional layers of nan-scaled metal lines in a higher level and the use of repeaters to maximize the performance, noise and reliability and to minimize the risk and cost.
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Jason J. Yao,Keh-Jeng Chang,Wei-Che Chuang,Jimmy S. Wang 대한전자공학회 2005 Journal of semiconductor technology and science Vol.5 No.4
With the advent of sub-90㎚ technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, lowpower, and small-form-factor consumer electronic systems running at multiple ㎓. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5㎜-long wires and 100 picoseconds for 15㎜-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of systemon- chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-㎓ SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.
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Yao Jason J.,Chang Keh-Jeng,Chuang Wei-Che,Wang, Jimmy S. The Institute of Electronics and Information Engin 2005 Journal of semiconductor technology and science Vol.5 No.4
With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.
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