http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement
Kim, Jong-Hoon,Lim, Ji-Hoon,Kim, Byungsub,Sim, Jae-Yoon,Park, Hong-June The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.2
An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20", 30", 40" FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a $0.13{\mu}m$ process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.
Kim, Kwangmin,Kang, Seokjoon,Sim, Jae-Yoon,Park, Hong-June,Kim, Byungsub IEEE 2018 IEEE transactions on very large scale integration Vol.26 No.12
<P>In this paper, we propose a search algorithm to find the worst operation scenario of a cross-point array of a phase-change random access memory to enable a precise read margin evaluation. The search algorithm utilizes a particle swarm optimization method to find the worst scenario quickly and efficiently. In an experiment, the proposed algorithm improves the search speed by <TEX>$39.3\times $</TEX> compared with the previous algorithm. With the improved search speed, the proposed algorithm could find the worst operation scenarios of large arrays whose worst operation scenarios had been only guessed before. In the experiment with a large array, the proposed algorithm proved that the worst high-resistance state read current can be <TEX>$36\times $</TEX> larger than the previous best guess. In the reliability test, the evaluation error of the worst read current found by the proposed algorithm is less than 0.2% with 99% probability. These results show that the proposed search algorithm can improve the precision and efficiency of the read margin evaluation in designing a cross-point phase-change memory array.</P>
An OTA with Positive Feedback Bias Control for Power Adaptation Proportional to Analog Workloads
Byungsub Kim,Jae-Yoon Sim,Hong-June Park 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.3
This paper reports an adaptive positive feedback bias control technique for operational transconductance amplifiers to adjust the bias current based on the output current monitored by a current replica circuit. This technique enables operational transconductance amplifiers to quickly adapt their power consumption to various analog workloads when they are configured with negative feedback. To prove the concept, a test voltage follower is fabricated in 0.5-μm CMOS technology. Measurement result shows that the power consumption of the test voltage follower is approximately linearly proportional to the load capacitance, the signal frequency, and the signal amplitude for sinusoidal inputs as well as square pulses.
An OTA with Positive Feedback Bias Control for Power Adaptation Proportional to Analog Workloads
Kim, Byungsub,Sim, Jae-Yoon,Park, Hong-June The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.3
This paper reports an adaptive positive feedback bias control technique for operational transconductance amplifiers to adjust the bias current based on the output current monitored by a current replica circuit. This technique enables operational transconductance amplifiers to quickly adapt their power consumption to various analog workloads when they are configured with negative feedback. To prove the concept, a test voltage follower is fabricated in $0.5-{\mu}m$ CMOS technology. Measurement result shows that the power consumption of the test voltage follower is approximately linearly proportional to the load capacitance, the signal frequency, and the signal amplitude for sinusoidal inputs as well as square pulses.
Yoon-Jee Kim,Jaehyun Park,Byungsub Kim,Jae-Yoon Sim,Hong-June Park 대한전자공학회 2020 IEIE Transactions on Smart Processing & Computing Vol.9 No.5
A fully differential readout integrated circuit (ROIC) is proposed to enhance SNR by using a micro electro mechanical system (MEMS) microphone pair. A differential clock is AC-coupled to the MEMS microphone pair as AC bias for chopper operation, while maintaining a high-voltage DC bias through high-resistance resistors for high sensitivity. The MEMS microphone pair connected to the fully differential ROIC amplifier with a demodulation chopper increased the measured SNRAW by 3.5~4.3dB compared to a single MEMS microphone with a chopper. The chopper operation applied to the pair of MEMS microphones reduced the measured audio band noise at the ROIC output by 14.8~16.5 times, compared to the no-chopper case. The fully differential ROIC consists of an amplifier, a demodulation chopper, a pair of resistor-capacitor low pass filters (RC-LPFs) and a unity-gain buffer. The ROIC implemented in a 0.35μm CMOS process takes a chip area of 2.5mm² and consumes 134μA at a supply voltage of 3.3V.
An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement
Jong-Hoon Kim,Ji-Hoon Lim,Byungsub Kim,Jae-Yoon Sim,Hong-June Park 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.2
An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20”, 30”, 40” FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a 0.13 μm process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.
Soo-Min Lee,Il-Min Yi,Hae-Kang Jung,Hyunbae Lee,Yong-Ju Kim,Yun-Saing Kim,Byungsub Kim,Jae-Yoon Sim,Hong-June Park IEEE 2014 IEEE journal of solid-state circuits Vol.49 No.11
<P>A low-energy single-ended duobinary transceiver is proposed for the point-to-point DRAM interface with an energy efficiency of 0.56 pJ/bit at 7 Gb/s. The transmitter power is reduced by decreasing the signal swing of transmission channel to 80 mV and replacing the multiplexer and the binary output driver in the transmitter by a duobinary output driver. A trans-impedance amplifier (TIA) is used at the receiver end of transmission channel. The TIA works as a receiver termination and also amplifies the input signal for subsequent processing. Analysis of the feedback loop delay and the nonlinearity of the TIA shows that they do not impose serious problems. The TIA output signal is applied to a duobinary-to-NRZ converter, which is implemented by using a direct feedback 1-tap DFE circuit with a tap-coefficient of 1.0. The reference voltage of the duobinary-to-NRZ converter is calibrated automatically to enable a small-swing signaling. The proposed transceiver chip in a 65 nm CMOS process works at 4.5 Gb/s with a 3' FR4 microstrip line, and at 7 Gb/s with a 0.6' FR4.</P>
Different behaviors of half-metallic ferromagnetism of Cr-doped AlN and InN
Kang, ByungSub,Lee, HaengKi,Kim, KyeongSup,Kang, HeeJae Royal Swedish Academy of Sciences 2009 Physica scripta Vol.79 No.2
<P>The electronic structure and magnetism are studied for the zinc-blende and wurtzite (Al,Cr)N, (Ga,Cr)N and (In,Cr)N by using the full potential linear muffin-tin orbital method. The energy gap (quasi-gap) in Cr-doped wurtzite InN decreases exponentially with increasing the Cr concentration from 0.027 to 0.166. The half-metallicity is retained in the whole range of concentrations considered, whereas for (Al,Cr)N, the half-metallic character disappears at a concentration of 0.166. The Cr magnetic moment in AlN is about 2.12–2.40μ<SUB>B</SUB> Cr atom<SUP>−1</SUP> with changing the Cr concentration, and for Cr in InN, it is a nearly constant value of 3.0 μ<SUB>B</SUB> Cr atom<SUP>−1</SUP>.</P>