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Image에 따른 효과적인 LCD 백라이트 Block 단위 Nonideality 및 Cross-talk Compensation
한원진(WonJin Han),유재희(JaeHee You) 大韓電子工學會 2011 電子工學會論文誌-SP (Signal processing) Vol.48 No.4
Backlight Profile과 Image Pixel의 Homogeneity 분석을 통한 Block 단위 LCD Backlight Nonideality 및 Crosstalk Compensation 방안이 제안되었다. Image에 따라 Block Size 및 연산에서 제외되는 Block 범위 그리고 연산에 고려되는 Backlight 범위를 최적화하여, 화질을 유지하면서 연산량을 최소화시켰다. 실제 영상을 바탕으로 하는 Simulation을 통해 제안된 Compensation 연산량과 화질이 평가되었다. Block based LCD backlight nonideality and crosstalk compensation methodologies are proposed based on the analysis of backlight profiles and image pixel homogeneity. Large computation complexity required in the conventional compensations is minimized without the degradation of image qualities by optimizing image block size, image area inside the block to be excluded from the compensation computation and the required backlight range to be computed. The optimization results of computation complexity as well as image qualities are verified for the proposed compensation by real image data simulations.
SOP Image SRAM Buffer용 다양한 데이터 패턴 병렬 테스트 회로
정규호(Kyuho Jeong),유재희(Jaehee You) 大韓電子工學會 2009 電子工學會論文誌-SD (Semiconductor and devices) Vol.46 No.9
System on panel 프레임 버퍼를 위한 메모리 셀 어레이와 주변회로가 설계되었다. 또한, system on panel 공정의 낮은 yield를 극복하기 위해, 블럭 단위의 parallel test 방안이 제안되었다. 기존의 메모리 테스트 보다 빠르게 fault detection이 가능하며, 다양한 embedded memory나 일반 SRAM 테스트 분야에도 적용 가능하다. 또한 기존의 다양한 test vector pattern이 그대로 적용될 수 있어 fault coverage가 높고, 최근의 추세인 hierarchical bit line과 divided word line 구조에도 적용될 수 있다. Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.
간단한 위상 보간기 기반의 스프레드 스펙트럼 클락 발생 기술
이경록(Kyoungrok Lee),유재희(Jaehee You),김종선(Jongsun Kim) 大韓電子工學會 2010 電子工學會論文誌-SD (Semiconductor and devices) Vol.47 No.10
본 논문에서는 전자기파 장애(EMI)의 감소를 위한 위상 보간기 기반의 새로운 스프레드 스펙트럼 클락 발생기(SSCG)를 제시한다. 제안하는 SSCG는 낮은 설계 복잡도와 저전력 및 작은 칩면적을 갖으며 삼각 주파수 변조를 이루기 위해 디지털적으로 조절 가능한 위상 보간 방식을 사용하였다. 이 새로운 SSCG는 듀티 싸이클 왜곡 없이 200㎒에서 ±2%의 센터-스프레드스펙트럼 범위를 갖는 시스템 클락을 발생시킬 수 있다. 이 위상 보간기 기반의 SSCG 회로는 200㎒에서 약 5.0 ㎽의 전력을 소모하고, 0.18-㎛ 1.8-V CMOS 공정을 사용하여 설계하여 검증하였으며 0.092㎟ 의 칩 면적을 차지한다. A compact phase interpolator (PI) based spread spectrum clock generator (SSCG) for electromagnetic interference (EMI) reduction is presented. The proposed SSCG utilizes a digitally controlled phase interpolation technique to achieve triangular frequency modulation with less design complexity and small power and area overhead. The novel SSCG can generate the system clock with a programmable center-spread spectrum range of up to +/- 2 % at 200 ㎒, while maintaining the clock duty cycle ratio without distortions. The PI-based SSCG has been designed and evaluated in 0.18-㎛ 1.8-V CMOS technology, which consumes about 5.0 ㎽ at 200㎒ and occupies a chip size of 0.092㎟ including a DLL.
柳在熙,裵埈徹 弘益大學校 科學技術硏究所 2002 科學技術硏究論文集 Vol.13 No.-
Based on Constant geometry Discrete cosine transform algorithm, an architecture with identical hardware cascaded by pipeline style, which is capable of high throughput as well as shape adaptive edge pel processing for object based coding is proposed. For shape adaptive DCT, input pels are fed into data buffer, appropriate pel input is shuffled with MUX, average of pel based on nearby pels is computed for pel padding and finally the outputs are shuffled for 8 X 8 matrix format for DCT post processing. The presented DCT architecture can be utilized for MPEG2 and MPEG4 codec by programming the presented padding hardware.
System on Panel Coprocessor Fault Detection Routine을 통한 효율적인 Redundancy Replacement 방안
柳在熙,李絃求 弘益大學校 科學技術硏究所 2004 科學技術硏究論文集 Vol.15 No.-
To meet increasing users' demand in portable system display panel such as less weight, power, size as well as more features, a fault tolerant image processing coprocessor integration on display panel with poly Si is proposed. Due to low yield of poly Si, the coprocessor integration needs high degree of fault tolerance for commercial use. This paper presents not only how to detect but also how to recover the faults in the coprocessor using a novel fault detection routine based on simultaneous main and the coprocessor execution and an efficient redundancy scheme. The proposed fault tolerance methodologies can play an important role in system on panel implementation to be realized in the near future