GF ( 2m ) 상의 산술연산기시스템 구성 논리 ( A Construction Theory of Arithmetic Operation Unit Systems over GF ( 2m ) )

박춘명,김흥수 대한전자공학회 1990 전자공학회논문지 Vol.27 No.6

모서리값 확장 그래프를 사용한 함수구성에 관한연구

박춘명,Park, Chun-Myoung 한국정보통신학회 2013 한국정보통신학회논문지 Vol.17 No.4

본 논문에서는 최근의 디지털논리시스템의 함수구성시에 도입되고 있는 그래프이론에 바탕을 둔 새로운 형태의 데이터구조 형태인 모서리값 확장 그래프를 추출하는 알고리즘을 제안하였다. 이를 위해 수학적 배경으로는 리터럴 함수와 리드 뮬러 확장에 대해 논의하였으며, 본 논문의 근간인 모서리 확장 그래프의 도출에 대해 논의하였다. 또한, 모서리 확장 그래프로부터 임의의 m치 n변수의 축약된 함수구성을 도출하는 알고리즘을 제안하였으며 이를 예에 적용하여 그 타당성을 보였다. 제안된 알고리즘의 규칙성을 고려하여 동일부분을 모듈화함으로써 일반성을 가짐을 보였다. In recently years, many digital logic systems based on graph theory are analyzed and synthesized. This paper presented a method of constructing the function using edge valued extension graph which is based on graph theory. The graph is applied to a new data structure. from binary graph which is recently used in constructing the digital logic systems based on the graph theory. We discuss the mathematical background of literal and reed-muller expansion, and we discuss the edge valued extension graph which is the key of this paper. Also, we propose the algorithms which is the function derivation based on the proposed edge valued extension graph. That is the function minimization method of the n-variables m-valued functions and showed that the algorithm had the regularity with module by which the same blocks were made concerning about the schematic property of the proposed algorithm.

모듈러技法에 基礎한 多値디지탈論理스위칭 函數의 回路設計에 관한 硏究

朴春明 충주대학교 산업대학원 1999 大學院論文輯 Vol.1 No.-

This paper presents a method of the circuit design of the multiple-valued digital logic switching functions based on the modular techniques. First of all,we introduce the necessity,background and concepts of the modular design techniques for the digital logic systems. Next, we discuss the definitions that are used in this paper. For the purpose of the circuit design for the multiple-valued digital logic switching functions, we discuss the extraction of the partion functions. Also we describe the construction method of the building block,that is called the modules, based on each partion functions. And we apply the proposed method to the example,we compare the results with the results of the earlier methods. In result, we decrese the control function, it means that we obtain the effective cost in the digital logic design for any other earlier methods. In the future research,we require the universal module that treat more partion functions and more compct module.

일천궁의 재배 기술 현황

박춘명 경북대학교 농업개발대학원 1995 最高農業經營者課程 論文集 Vol.- No.1

Galois體上에서의 線形多値理論 디지탈시스템 構成

朴春明 충주대학교 1997 한국교통대학교 논문집 Vol.32 No.2

This paper presents a method of constructing the Linear Multiple-Valued Logic Digital Systems (LMVLDS) over Galois Fields. The proposed method is as follows. First of all, we extract the input/output relationship of linear characteristics for the given digital logic systems. Next, we convert the input/output relationship to Directed Cyclic Graph(DCG) using basic gates adder and coefficient multiplier that are defined by mathematical properties in Galois fields. Also, we propose the new factorization method for matrix characteristics equation that represents the relationship of the input/output characteristics. The proposed method has the generalization and regularity. Also, the proposed method is possibly applied to any prime number multiplication expression.

결정도에 기초한 다중출력조합디지털논리시스템

박춘명 한국정보통신학회 2005 한국정보통신학회논문지 Vol.9 No.7

This paper presents a design method for multiple-output combinational digital logic systems using time domain based on multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The CMTEDDs represents extension valued multiple-output functions, while TDBM systems transmit several signals on a single lines. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one. 본 논문에서는 TDBM과 CMTEDD를 사용하여 다중출력조합디지털논리시스템 설계방법의 한가지를 제안하였다. 또한, CBDD와 CMTEDD를 기반으로 최종 조합디지털논리시스템 구성을 멀티플렉서를 사용하여 구현하였다. 제안한 방법은 기존의 방법에 비해 모듈사이의 내부결선을 효과적으로 줄일 수 있으며 입력변수의 쌍과 출력함수의 쌍에 의해 게이트 수를 줄일 수 있는 장점이 있다.

GF(P)上의 多値論理順次 디지탈시스템 構成에 관한 硏究

朴春明 忠州大學校 1999 한국교통대학교 논문집 Vol.34 No.2

This paper presents a method for constructing thr multiple-valued logic sequential digital systems over the Galois Field GF(Pm) Fist, we assign all elements in GF(Pm) tl P-valued digit codes using mathematical properties of Galois Field GF(Pm) Also, we discuss the operationl charateristics and properties of the building block T-gate that is used for realizing the multiple-valued logic sequential digital systems over the Galois Field GF(Pm) Then, we realize the multiple-valued logic sequential digital systems with and without feed-back 1) The multipe-valued logic sequential digital systems with feed-back is constructed by using only T-gate from state-transition diagram expressing the information of the sequential logic digital systems. 2)The multilpe-valued logic sequential digital systems without feed-back is constructed by following steps. First, we assign the states in state-transition diagram to state P-valued digit codes,then obtain the states function and predecessor table that explaning the relation ship between present states and previos state.Next, we obtained the next-stat function from state function and predecessor table. Finally we realize the circuit using T-gate and decoder. The proposed method for construcing the multiple-valued logic sequential digital systems over the Galois Fiel GF(Pm) is regularity and extensibility than earier methods.

Galois體 GF(P^m)上의 算術演算器 시스템 構成에 관한 硏究

朴春明 충주대 산업과학기술연구소 1996 産業科學論文集 Vol.4 No.-

This paper propose the method of constructing the arithmetic operation unit system that perform binary operation(addition operation and multiplication operation) over Galois Field GF(Pm). The addition operation over Galois Field is comparatively simple because that addition operation is analysed by digit modP summation independantly. But in multiplication operation, generate maximum 2m -2 degree of αk terms, therefore decrese k into m -1 degree using primitive irreducible polynomial. We propose two method of control signal generatation for perform above decrese process. One method is the combinational logic expression and the other method is universal control signal generation. The proposed arithmetic operation unit systems following steps. First of all, we obtain algorithms for addition operation and multiplication operation based on the mathematical properties over Galois Field GF(Pm), next construct basic cell for A-cell and M-cell using T-gate and ModP cyclic gate. Finally construct adder module and multiplication module over Galois Field GF(Pm) after synthesize αk generation module and control signal CSt generation module with above A -cell and M-cell. Then, we propose the future research and prospects.

決定圖에 基礎한 多重出力 組合디지털論理시스템 設計

朴春明 충주대 2001 한국교통대학교 논문집 Vol.36 No.2

This paper presents a design method for multiple-output combinational digital logic systems using time domain based multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD).The CMTEDDs represents extension valued multiple-output functions, while TDBM systems transmit several signals on a single lines.The proposed method can reduce the 1) hardware, 2) logic levels and 3) pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs.The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes.In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

그래프에 기초한 스위칭함수 구현

박춘명,Park, Chun-Myoung 한국정보통신학회 2011 한국정보통신학회논문지 Vol.15 No.9

본 논문에서는 그래프에 기초하여 유한체상의 스위칭함수를 도출하는 알고리즘과 이를 바탕으로 스위칭함수를 회로로 구현하는 방법을 제안하였다. 방향성그래프의 경로 수로부터 행렬방정식을 유도한 후에 이에 따른 스위칭 함수회로설계 알고리즘을 제안하였으며, 설계된 회로와 함께 방향성 그래프의 특성을 만족할 수 있게 노드들에 대한 코드를 할당하는 알고리즘을 제안하였다. 본 논문에서 제안한 알고리즘을 통해 설계한 스위칭함수회로는 기존의 방법에 비해 좀 더 최적화된 스위칭함수회로를 구현할 수 있었으며, 제안한 스위칭함수회로설계 알고리즘을 통해 임의의 자연수의 경로 수를 갖는 방향성 그래프에 대한 설계가 가능하였다. 또한, 입출력단자 수의 감소, 회로구성의 간략화, 연산속도의 향상과 비용감소 등의 이점이 있었다. This paper proposes the method of switching function implementation using switching function extraction based on graph over finite fields. After we deduce the matrix equation from path number of directional graph, we propose the switching function circuit algorithm, also we propose the code assignment algorithm for nodes which is satisfied the directional graph characteristics with designed circuits. We can implement more optimal switching function compare with former algorithm, also we can design the switching function circuit which have any natural number path through the proposed switching function circuit implementation algorithms. Also the proposed switching function implementation using graph theory over finite fields have decrement number of input-output, circuit construction simplification, increment arithmetic speed and decrement cost etc.