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고성능 PMOSFET을 위한 Ni-silicide와 p+ Source/drain 사이의 Barrier Height 감소
공선규,장잉잉,박기영,이세광,정순연,신홍식,이가원,왕진석,이희덕,Kong, Sun-Kyu,Zhang, Ying-Ying,Park, Kee-Young,Li, Shi-Guang,Jung, Soon-Yen,Shin, Hong-Sik,Lee, Ga-Won,Wang, Jin-Suk,Lee, Hi-Deok 한국전기전자재료학회 2009 전기전자재료학회논문지 Vol.22 No.6
In this paper, barrier height between Ni-silicide and source/drain is reduced utilizing Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. It is shown that the barrier height is decreased by Pd incorporation and is dependent on the Pd thickness. Therefore, Ni-silicide using the Pd stacked structure is promising for high performance nano-cale PMOSFET.