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Visible Wavelength Photonic Insulator for Enhancing LED Light Emission
Ryoo, Kwangki,Lee, Jeong Bong The Korea Institute of Information and Commucation 2015 Journal of information and communication convergen Vol.13 No.1
We report design and simulation of a two-dimensional (2D) silicon-based nanophotonic crystal as an optical insulator to enhance the light emission efficiency of light-emitting diodes (LEDs). The device was designed in a manner that a triangular array silicon photonic crystal light insulator has a square trench in the middle where LED can be placed. By varying the normalized radius in the range of 0.3-0.5 using plane wave expansion method (PWEM), we found that the normalized radius of 0.45 creates a large band gap for transverse electric (TE) polarization. Subsequently a series of light propagation simulation were carried out using 2D and three-dimensional (3D) finite-difference time-domain (FDTD). The designed silicon-based light insulator device shows optical characteristics of a region in which light propagation was forbidden in the horizontal plane for TE light with most of the visible light spectrum in the wavelength range of 450 nm to 600 nm.
High-Aspect-Ratio Nanoscale Patterning in a Negative Tone Photoresist
Ryoo, Kwangki,Lee, Jeong Bong The Korea Institute of Information and Commucation 2015 Journal of information and communication convergen Vol.13 No.1
The demand for high-aspect-ratio structures has been increasing in the field of semiconductors and other applications. Here, we present the commercially available negative-tone SU-8 as a potential resist that can be used for direct patterning of high-aspect-ratio structures at the submicron scale and the nanoscale. Such resist patterns can be used as polymeric molds to create high-aspect-ratio metallic submicron and nanoscale structures by using electroplating. Compared with poly (methyl methacrylate) (PMMA), we found that the negative tone resist required an exposure dose that was less than that of PMMA of equal thickness by a factor of 100-150. Patterning of up to 4:1 aspect ratio SU-8 structures with a minimum feature size of 500 nm was demonstrated. In addition, nanoimprint lithography was studied to further extend the aspect ratio to realize a minimum feature size of less than 10 nm with an extremely high aspect ratio in the negative resist.
A Performance-Oriented Intra-Prediction Hardware Design for H.264/AVC
Jin, Xianzhe,Ryoo, Kwangki The Korea Institute of Information and Commucation 2013 Journal of information and communication convergen Vol.11 No.1
In this paper, we propose a parallel intra-operation unit and a memory architecture for improving the performance of intra-prediction, which utilizes spatial correlation in an image to predict the blocks and contains 17 prediction modes in total. The design is targeted for portable devices applying H.264/AVC decoders. For boosting the performance of the proposed design, we adopt a parallel intra-operation unit that can achieve the prediction of 16 neighboring pixels at the same time. In the best case, it can achieve the computation of one luma $16{\times}16$ block within 16 cycles. For one luma $4{\times}4$ block, a mere one cycle is needed to finish the process of computation. Compared with the previous designs, the average cycle reduction rate is 78.01%, and the gate count is slightly reduced. The design is synthesized with the MagnaChip $0.18{mu}m$ library and can run at 125 MHz.
An Efficient Interpolation Hardware Architecture for HEVC Inter-Prediction Decoding
Jin, Xianzhe,Ryoo, Kwangki The Korea Institute of Information and Commucation 2013 Journal of information and communication convergen Vol.11 No.2
This paper proposes an efficient hardware architecture for high efficiency video coding (HEVC), which is the next generation video compression standard. It adopts several new coding techniques to reduce the bit rate by about 50% compared with the previous one. Unlike the previous H.264/AVC 6-tap interpolation filter, in HEVC, a one-dimensional seven-tap and eight-tap filter is adopted for luma interpolation, but it also increases the complexity and gate area in hardware implementation. In this paper, we propose a parallel architecture to boost the interpolation performance, achieving a luma $4{\times}4$ block interpolation in 2-4 cycles. The proposed architecture contains shared operations reducing the gate count increased due to the parallel architecture. This makes the area efficiency better than the previous design, in the best case, with the performance improved by about 75.15%. It is synthesized with the MagnaChip $0.18{\mu}m$ library and can reach the maximum frequency of 200 MHz.
OpenRISC Core-based SoC Platform Design and Verification
Younghoon Bin,Kwangki Ryoo 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
This paper describes a synthesizable OpenRISC-based SoC platform developed. The platform includes a CPU (OpenRISC 1200), some basic peripherals (on-chip RAM, GPIO, UART, debug interface, VGA controller) and WISHBONE onchip interconnect. The platform uses a set of development environment (compiler, assembler, debugger and RTOS) that is built for system debugging and software development. Designed SoC and IPs are verified with commercial logic simulator and prototyped using Xilinx FPGA development board. SoC platform is implemented in Spartan3 FPGA and verified through some test application programs compiled with or1200 cross-compiler.
Shrink Generator-based Strong PUF Architecture with Improved Uniqueness and Reliability on an FPGA
Guard Kanda,Kwangki Ryoo 대한전자공학회 2023 Journal of semiconductor technology and science Vol.23 No.1
Silicon-based Physically Unclonable Functions (PUFs) are a source of physical security primitive that is either implemented on ASICs or FPGAs. A class of these security primitives that provide an exponentially large set of Challenge-Response Pairs (CRPs) is termed Strong PUF. That notwithstanding, the Arbiter and Feedforward Arbiter PUFs which are traditionally Strong PUFs, are not suitable for FPGA implementation. In this paper, a newly proposed PUF architecture that improves on the existing Configurable Ring Oscillator (CRO) PUF by increasing its dynamic configurability and its level of entropy is presented. To maintain the exponentially large set of CRPs, the Shrink Generator is applied to the traditionally Weak CRO-PUF. The proposed design is implemented and tested on a spartan-6 FPGA board using the Xilinx ISE tool. The proposed architecture demonstrates a uniqueness of 50.01% and is 96.43% reliable.
The Design of Cache Architecture in 32-bit RISC for the Performance Improvement
Hongkyun Jung,Kwangki Ryoo 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
In this paper, two-way set-associative cache architecture is proposed in 32-bit RISC-based SoC for the performance improvement. Two-way set-associative cache has lower miss rate than direct-mapped cache. Direct-mapped cache in previous 32-bit RISC was modified into two-way associative cache. The proposed architecture is verified on HDL simulator and is tested on the program that manages student information. The result shows that the total number of clocks decreased by 5545 in the executed program.