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RISS 인기검색어
- 검색키워드
- 저자 : ( Dennis Agyemanh Nana Gookyi ) (검색결과 4 건)
- 무료
- 기관 내 무료
- 유료
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Selecting a Synthesizable RISC-V Processor Core for Low-cost Hardware Devices
Gookyi, Dennis Agyemanh Nana,Ryoo, Kwangki Korea Information Processing Society 2019 Journal of information processing systems Vol.15 No.6
The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is made possible because sensing and data collection devices have been given computing and communication capabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet they are severely constrained in terms of memory capacitance, hardware area, and power consumption. With the increase in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handle control, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-cost devices is to examine the hardware resource utilization to make sure that it fulfills the requirements of the device. This paper gives an analysis of the hardware resource usage of ten synthesizable processors that implement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All the ten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports are extracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.
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The Hardware Implementation of NIST Lightweight Cryptographic Candidate SpoC for loT Devices
Dennis Agyemanh Nana Gookyi,Kwangki Ryoo ASCONS 2021 IJASC Vol.3 No.1
Background/Objectives: This paper presents the hardware implementation of SpoC Lightweight Cryptography (LWC) candidate for low-cost devices. Methods/Statistical analysis: The proposed hardware implementation of the SpoC Authenticated Encryption with Associated Data (AEAD) is capable of both encryption and decryption. The design was implemented on the Virtex-4 Field FPGA using Xilinx ISE Design Suite. The synthesis results reported 951 slices at 246.61 MHz maximum clock frequency. The encryption and decryption routines take 589 and 590 cycles. Findings: This work used 30% fewer LUTs for both encryption and decryption as compared to the existing work. The decrease in area in this work is a result of the optimization of the implementation for low-cost devices while the existing work implemented the basic iterative architecture without optimizing. This work achieved almost two times the frequency of the existing SpoC implementation. The existing SpoC implementation used 150 fewer cycles as compared to this work. This is because this work implemented the SpoC using extra registers in other to reduce the critical path which increases the frequency. Improvements/Applications: For future works, the proposed SpoC AEAD will be combined with other security protocols to form a lightweight cryptographic System-on-Chip (SoC).
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( Dennis Agyemanh Nana Gookyi ),( Guard Kanda ),( Kwangki Ryoo ) 한국정보처리학회 2021 Journal of information processing systems Vol.17 No.2
In January 2013, the National Institute of Standards and Technology (NIST) announced the CAESAR (Competition for Authenticated Encryption: Security, Applicability, and Robustness) contest to identify authenticated ciphers that are suitable for a wide range of applications. A total of 57 submissions made it into the first round of the competition out of which 6 were announced as winners in March 2019. In the process of the competition, NIST realized that most of the authenticated ciphers submitted were not suitable for resource-constrained devices used as end nodes in the Internet-of-Things (IoT) platform. For that matter, the NIST Lightweight Cryptography Standardization Process was set up to identify authenticated encryption and hashing algorithms for IoT devices. The call for submissions was initiated in 2018 and in April 2019, 56 submissions made it into the first round of the competition. In August 2019, 32 out of the 56 submissions were selected for the second round which is due to end in the year 2021. This work surveys the 32 authenticated encryption schemes that made it into the second round of the NIST lightweight cryptography standardization process. The paper presents an easy-to-understand comparative overview of the recommended parameters, primitives, mode of operation, features, security parameter, and hardware/software performance of the 32 candidate algorithms. The paper goes further by discussing the challenges of the Lightweight Cryptography Standardization Process and provides some suitable recommendations.
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Selecting a Synthesizable RISC-V Processor Core for Low-cost Hardware Devices
Dennis Agyemanh Nana Gookyi,류광기 한국정보처리학회 2019 Journal of information processing systems Vol.15 No.6
The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is madepossible because sensing and data collection devices have been given computing and communicationcapabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet theyare severely constrained in terms of memory capacitance, hardware area, and power consumption. With theincrease in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handlecontrol, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-costdevices is to examine the hardware resource utilization to make sure that it fulfills the requirements of thedevice. This paper gives an analysis of the hardware resource usage of ten synthesizable processors thatimplement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All theten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports areextracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.
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