http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
- 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
- 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
RISS 인기검색어
- 검색키워드
- 저자 : Zhanpeng Jiang (검색결과 2 건)
- 무료
- 기관 내 무료
- 유료
-
Design of a ROM-Less Direct Digital Frequency Synthesizer on FPGA
Zhanpeng Jiang,Rui Xu,Hai Huang,Changchun Dong 보안공학연구지원센터 2015 International Journal of Signal Processing, Image Vol.8 No.5
DDFS (Direct Digital Frequency Synthesizer) is a new technique of frequency synthesizes which introduces the advanced digital processing theory into frequency synthesis. A direct digital frequency synthesizer is composed of a phase accumulator, an adder, an ROM for wave pattern saving, a D/A converter and a LPF (low pass filter). With the rapid development of VLSI, the speed of algorithm is required increasingly higher. This paper proposes a new frequency synthesizer by improving the structure of data storage which ensures the accuracy and speed. Rotation method was used to resolve the expected angle into many small rotation angles and sting wave symmetry principle was used to resolve the string wave. From point to area, the values in one quadrant were calculated and sampled and then the data was saved in ROM. Under the control of frequency, the data in ROM was read and then transferred to the D/A converter chip and the following low pass filter to achieve frequency synthesize. This algorithm could reduce the usage of ROM to increase the calculation efficiency.
-
An Optimization of CORDIC Algorithm and FPGA Implementation
Rui Xu,Zhanpeng Jiang,Hai Huang,Changchun Dong 보안공학연구지원센터 2015 International Journal of Hybrid Information Techno Vol.8 No.6
ASIC and FPGA ASIC and FPGA are considered to be the ideal platform for special fast calculations because of the hardware structure, and how to achieve computational algorithm by is the hotpot of research. The CORDIC (Coordinate Rotational Digital Computer) can break the basis functions down to operations of shift and addition or subtraction, which can be used to lay the foundation for the realization of complex logic. But the functions selected by traditional CODIC for angle encoding are too complex, which will lead to some problems, such as too much of area consumption and large delay. In this paper, an optimization of CORDIC algorithm are proposed, which reduce the consumption of Adders and comparators, decrease the complexity and delay of the algorithm implement in hardware. The proposed algorithms are modeled in Verilog Hardware Description Language and implemented with FPGA. The simulation results show that the functions of sine and cosine are realized successfully, and the proposed algorithm not only improves the computation speed but also reduces the system hardware resources.
연관 검색어 추천
이 검색어로 많이 본 자료
활용도 높은 자료
