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Structure of High-Speed Modulo Multiplier Oriented to Repeated Operation
Tadamichi Kudou,Yoshitaka Tsunekawa 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
A high-speed modulo multiplier using redundant representations is presented. It is oriented to repeated operations such as public key cryptosystems which preform repeated modulo multiplications. First, to implement a high-speed modulo multiplier, we show two approaches for radix-2 operations to perform each operations simultaneously. Second, these approaches are applied to radix-4 operations to reduce clock cycles. As a result, the speed of the proposed structure becomes over twice faster than the conventional structures.
High-Performance Pipelined VLSI Architecture of the LMS Adaptive Filter
Kyo Takahashi,Shingo Sato,Yoshitaka Tsunekawa 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
This paper presents a high-performance pipelined VLSI architecture of the LMS adaptive filter derived by a cut-set retiming technique (CSRT). The architecture has a minimum output latency, high sampling rate, small hardware, and low power dissipation, simultaneously.