Risk Assessment of 5-Chloro-2-Methylisothiazol-3(2H)-One/2-Methylisothiazol-3(2H)-One (CMIT/MIT) Used as a Preservative in Cosmetics

Kim, Min Kook,Kim, Kyu-Bong,Lee, Joo Young,Kwack, Seung Jun,Kwon, Yong Chan,Kang, Ji Soo,Kim, Hyung Sik,Lee, Byung-Mu Korean Society of ToxicologyKorea Environmental Mu 2019 Toxicological Research Vol.35 No.2

The mixture of 5-chloro-2-methylisothiazol-3(2H)-one (CMIT) and 2-methylisothiazol-3(2H)-one (MIT), CMIT/MIT, is a preservative in cosmetics. CMIT/MIT is a highly effective preservative; however, it is also a commonly known skin sensitizer. Therefore, in the present study, a risk assessment for safety management of CMIT/MIT was conducted on products containing 0.0015% of CMIT/MIT, which is the maximum MIT level allowed in current products. The no observed adverse effect level (NOAEL) for CMIT/MIT was 2.8 mg/kg bw/day obtained from a two-generation reproductive toxicity test, and the skin sensitization toxicity standard value for CMIT/MIT, or the no expected sensitization induction level (NESIL), was $1.25{\mu}g/cm^2/day$ in humans. According to a calculation of body exposure to cosmetics use, the systemic exposure dosage (SED) was calculated as 0.00423 mg/kg bw/day when leave-on and rinse-off products were considered. Additionally, the consumer exposure level (CEL) amounted to $0.77512{\mu}g/cm^2/day$ for all representative cosmetics and $0.00584{\mu}g/cm^2/day$ for rinse-off products only. As a result, the non-cancer margin of safety (MOS) was calculated as 633, and CMIT/MIT was determined to be safe when all representative cosmetics were evaluated. In addition, the skin sensitization acceptable exposure level (AEL)/CEL was calculated as 0.00538 for all representative cosmetics and 2.14225 for rinse-off products; thus, CMIT/MIT was considered a skin sensitizer when all representative cosmetics were evaluated. Current regulations indicate that CMIT/MIT can only be used at concentrations 0.0015% or less and is prohibited from use in other cosmetics products. According to the results of this risk assessment, the CMIT/MIT regulatory values currently used in cosmetics are evaluated as appropriate.

Fabrication of a Bottom Electrode for a Nano-scale Beam Resonator Using Backside Exposure with a Self-aligned Metal Mask

Lee, Yong-Seok,Jang, Yun-Ho,Bang, Yong-Seung,Kim, Jung-Mu,Kim, Jong-Man,Kim, Yong-Kweon The Korean Institute of Electrical Engineers 2009 Journal of Electrical Engineering & Technology Vol.4 No.4

In this paper, we describe a self-aligned fabrication method for a nano-patterned bottom electrode using flood exposure from the backside. Misalignments between layers could cause the final devices to fail after the fabrication of the nano-scale bottom electrodes. A self-alignment was exploited to embed the bottom electrode inside the glass substrate. Aluminum patterns act as a dry etching mask to fabricate glass trenches as well as a self-aligned photomask during the flood exposure from the backside. The patterned photoresist (PR) has a negative sidewall slope using the flood exposure. The sidewall slopes of the glass trench and the patterned PR were $54.00^{\circ}$ and $63.47^{\circ}$, respectively. The negative sidewall enables an embedment of a gold layer inside $0.7{\mu}m$ wide glass trenches. Gold residues on the trench edges were removed by the additional flood exposure with wet etching. The sidewall slopes of the patterned PR are related to the slopes of the glass trenches. Nano-scale bottom electrodes inside the glass trenches will be used in beam resonators operating at high resonant frequencies.

MCU용 Fast 256Kb EEPROM 설계

김용호,박헌,박무훈,하판봉,김영희,Kim, Yong-Ho,Park, Heon,Park, Mu-Hun,Ha, Pan-Bong,Kim, Young-Hee 한국정보통신학회 2015 한국정보통신학회논문지 Vol.19 No.3

본 논문에서는 MCU(Micro Controller Unit) IC를 위한 50ns 256Kb EEPROM 회로를 설계하였다. 설계된 EEPROM IP는 기준전압을 이용한 차동증폭기 형태의 DB(Data Bus) 센싱 회로를 제안하여 읽기 동작시 데이터 센싱 속도를 빠르게 하였으며, DB를 8등분한 Distributed DB 구조를 적용하여 DB의 기생 커패시턴스 성분을 줄여 DB의 스위칭 속도를 높였다. 또한 기존의 RD 스위치 회로에서 5V 스위치 NMOS 트랜지스터를 제거함으로써 읽기 동작 시 BL의 프리차징 시간을 줄여 액세스 시간을 줄였고 데이터 센싱 시 DB 전압과 기준전압 간의 전압차 ${\Delta}V$를 0.2VDD 정도 확보하여 출력 데이터의 신뢰도를 높였다. 매그나칩반도체 $0.18{\mu}m$ EEPROM 공정으로 설계된 256Kb EEPROM IP의 액세스 시간은 45.8ns 이며 레이아웃 면적은 $1571.625{\mu}m{\times}798.540{\mu}m$이다. In this paper, a 50ns 256-kb EEPROM IP for MCU (micro controller unit) ICs is designed. The speed of data sensing is increased in the read mode by using a proposed DB sensing circuit of differential amplifier type which uses the reference voltage, and the switching speed is also increased by reducing the total DB parasitic capacitance as a distributed DB structure is separated into eight. Also, the access time is reduced reducing a precharging time of BL in the read mode removing a 5V NMOS transistor in the conventional RD switch, and the reliability of output data can be secured by obtaining the differential voltage (${\Delta}V$) between the DB and the reference voltages as 0.2*VDD. The access time of the designed 256-kb EEPROM IP is 45.8ns and the layout size is $1571.625{\mu}m{\times}798.540{\mu}m$ based on MagnaChip's $0.18{\mu}m$ EEPROM process.

동기식 256-bit OTP 메모리 설계

이용진,김태훈,심외용,박무훈,하판봉,김영희,Li, Long-Zhen,Kim, Tae-Hoon,Shim, Oe-Yong,Park, Mu-Hun,Ha, Pan-Bong,Kim, Young-Hee 한국정보통신학회 2008 한국정보통신학회논문지 Vol.12 No.7

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$. 본 논문에서는 자동차 전장용 Power IC, 디스플레이 구동 칩, CMOS 이미지 센서 등의 응용분야에서 필요로 하는 동기식 256-bit OTP(one-time programmable) 메모리를 설계하였다. 동기식 256-bit OTP 메모리의 셀은 고전압 차단 트랜지스터 없이 안티퓨즈인 NMOS 커패시터와 액세스 트랜지스터로 구성되어 있다. 기존의 3종류의 전원 전압을 사용하는 대신 로직 전원 전압인 VDD(=1.5V)와 외부 프로그램 전압인 VPPE(=5.5V)를 사용하므로 부가적인 차단 트랜지스터의 게이트 바이어스 전압 회로를 제거하였다. 그리고 프로그램시 전류 제한 없이 전압 구동을 하는 경우 안티퓨즈의 ON 저항 값과 공정 변동에 따라 프로그램 할 셀의 부하 전류가 증가한다. 그러므로 프로그램 전압은 VPP 전원 선에서의 저항성 전압 감소로 인해 상대적으로 증가하는 문제가 있다. 그래서 본 논문에서는 전압 구동 대신 전류 구동방식을 사용하여 OTP 셀을 프로그램 할 때 일정한 부하전류가 흐르게 한다. 그래서 웨이퍼 측정 결과 VPPE 전압은 5.9V에서 5.5V로 0.4V 정도 낮출 수 있도록 하였다. 또한 기존의 전류 감지 증폭기 대신 Clocked 인버터를 사용한 감지 증폭기를 사용하여 회로를 단순화시켰다. 동기식 256-bit OTP IP는 매그나칩 반도체 $0.13{\mu}m$ 공정을 이용하여 설계하였으며, 레이아웃 면적은 $298.4{\times}3.14{\mu}m2$이다.

저전압 SoC용 밴드갭 기준 전압 발생기 회로 설계

이태영,이재형,김종희,심외용,김태훈,박무훈,하판봉,김영희,Lee, Tae-Young,Lee, Jae-Hyung,Kim, Jong-Hee,Shim, Oe-Yong,Kim, Tae-Hoon,Park, Mu-Hun,Ha, Pan-Bong,Kim, Young-Hee 한국정보통신학회 2008 한국정보통신학회논문지 Vol.12 No.1

The band-gap reference voltage generator which can be operated by low voltage is proposed in this paper. The proposed BGR circuit can be realized in logic process by using parasitic NPN BJTs because a $Low-V_T$ transistors are not necessary. The proposed BGR circuit is designed and fabricated using $0.18{\mu}m$ triple-well process. The mean voltage of measured VREF is 0.72V and the three sigma$(3{\sigma})$ is 45.69mv. 본 논문에서는 $Low-V_T$ 트랜지스터가 필요 없는 로직공정으로 Parasitic NPN BJT를 이용하여 저 전압에서 동작 가능한 밴드갭 기준전압 발생기 회로를 제안하였다. $0.18{\mu}m$ triple-well 공정을 사용한 BGR회로를 측정 한 결과 VREF의 평균전압은 0.72V $3{\sigma}$는 45.69mV로 양호하게 측정되었다.

관계 마케팅이 마케팅 생산성에 미치는 영향에 관한 실증 연구 : 이동통신산업을 중심으로

김용한,배무언 한국생산성학회 2004 生産性論集 Vol.18 No.1

This Paper analyzed the impact of relationship marketing on marketing productivity in the mobile telephone industry. For this paper, we measure the service quality for the user of mobile phones based on the satisfaction of relationship marketing with questionnaire. For our research, the SERVEQUAL, modeled by Zaithaml et a1.(1988), is used to find out the service failure, and the questionnaire developed by Crosby et al.(1980) and Morgan and Hunt(1994) is employed to check the customer satisfaction for relationship marketing. With this data, we analyse the impact of relationship satisfaction on negative customer behaviors, such as the blame, the customer exit and the Word of Mouth. For this analysis, AMOS 4.0 was used to check the cause-effect relationship among them. As a result, the quality of relationship marketing is negatively affected by the blame, the customer exit and the Word of Mouth. Therefore, relationship marketing plays a potentially significant role in increasing marketing productivity.

Bi_2Sr_2Ca_(n-1)Cu_nO_y(n=1, 2, 3)의 열기전력 측정연구

김용민,최무용 성균관대학교 기초과학연구소 1989 論文集 Vol.40 No.2

We have measured the thermopower of three phases of Bi_2Sr_2Ca_(n-1)Cu_nO_y for n = 1, 2, 3. The thermopower is found to he larger when n is bigger and its temperature derivative dS/dT is negative irrespective of phases. For n=1, we find that the thermopower itself is negative for all the temperature range above 10K, and when the same sample has been baked in vacuum at 600℃, thermopower vs. temperature curve shows a broad positive peak similar to those seen in rare-earth high-Tc superconductors. Considering these experimental fact, the suggestion that the charge carriers in these materials are holes may be seriously challanged. We have considered a two-band model as an alternative where holes and electrons coexsist as charge carriers.

성인 IgA 신병증의 임상적 고찰

김영학,권용은,허경무,윤채중,김종인,김건영,배학연,정종훈 조선의대 1998 The Medical Journal of Chosun University Vol.23 No.1

전자선 리토그래피 방법을 이용한 나노 구조 제조

김철균,최무용 성균관대학교 기초과학연구소 1998 論文集 Vol.49 No.-

In order to investigate the quantum-mechanical phenomena in mesoscopic systems, it is necessary to fabricate nano-scale structures. By using the electron-beam-direct-writing method and the lift-off method, we have successfully fabricated the quantum-dot gate structure with the gate width of 275 nm on a Si substrate. It is found that the optimal condition for writing the quantum-dot pattern on a 2,000Å-thick 4% - PMMA photo-resist is 90 seconds of develop time and 300 μC/㎠ of dose. It is also found that the optimal condition depends on geometry of nanostructure. It is necessary to find a new optimal condition for a pattern with a different geometry.

새우 乾燥 ·貯藏中의 品質 및 TBA價의 變化

김무남,전순실,김용주 順天大學校 1994 論文集 Vol.13 No.1

건조 온도를 25℃, 45℃로 달리한 건조새우의 건조 과정 중의 수분 함량, TBA가, 갈변반응과 온도, 수분 활성을 달리하여 저장하였을 때의 지방 산화를 비교 검토하였으며, 정온 저장 및 35/55℃ square wave형 변온 조건하에서 저장하였을 때의 TBA가를 조사하였다. 25℃, 45℃에서 건조 온도를 달리하여 건조하였을 경우 건조 과정 중 수분함량은 25℃가 높았으며 TBA가, 갈변도는 25℃의 경우가 낮게 나타났다. 저장 중 지방 산화는 변온 조건 (35/55℃)에서 저장하였을 경우는 그중간 온도 인 45℃보다 TBA가 높게 나타났다. □The changes of moisture content, TBA values and browning reaction were investigated during drying and storage of dried shrimp samples. The temperature conditions of drying process were 25℃, 45℃ and then the samples was controlled at Aw 0.33, 0.44, 0.52 and 0.65 using saturated salt solution and then stored at 35,45 and 55℃. In addition a storage study was done under a square-wave fluctuation from 35℃ to 55℃ with 7 days interval. The moisture contents of dried shrimp at 25℃ was higher than that dried at 45℃. TBA values and non-enzymatic browning reaction of dried shrimp at 25℃ were lower than those dried at 45℃. The TBA value of dried shrimp at non-steady storage(35/55℃)were higher than those stored at steady state(45℃).