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Mismatch-tolerant Capacitor Array Structure for Junction-splitting SAR Analog-to-digital Conversion
Youngjoo Lee,Taehyoun Oh,In-Cheol Park 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.3
A new junction-splitting based SAR ADC with a redundant searching capacitor array structure in 0.13 ㎛ CMOS process to alleviate capacitor mismatch effects, is presented. The normalized average power has a factor of 0.35 to the conventional SAR ADC at 10-bit conversion accuracy. Statistical experiments show the number of missing codes resulting from the mismatch reduces by 95% for 3% unit-capacitor mismatch ratio, while keeping the conversion energy to that of the conventional JS capacitor array.
Mismatch-tolerant Capacitor Array Structure for Junction-splitting SAR Analog-to-digital Conversion
Lee, Youngjoo,Oh, Taehyoun,Park, In-Cheol The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.3
A new junction-splitting based SAR ADC with a redundant searching capacitor array structure in $0.13{\mu}m$ CMOS process to alleviate capacitor mismatch effects, is presented. The normalized average power has a factor of 0.35 to the conventional SAR ADC at 10-bit conversion accuracy. Statistical experiments show the number of missing codes resulting from the mismatch reduces by 95% for 3% unit-capacitor mismatch ratio, while keeping the conversion energy to that of the conventional JS capacitor array.
Sanggeun Lee,Taehyoun Oh 대한전자공학회 2021 Journal of semiconductor technology and science Vol.21 No.2
A system level power/jitter reduction technique of all-digital phase locked loop (ADPLL) design has been developed. The architecture to memorize the repetitive control signal pattern of digitally-controlled oscillator (DCO) during lock state and to regenerate the pattern, achieve the reduced power consumption compared to conventional mode from 14.4 mW to 9.51 mW in 1.0 V supply at 12.2 GHz and concurrently reduce jitter from 1.86 ps to 1.56 ps. The prototype PLL has been fabricated in 65 nm CMOS process and occupies 0.16 ㎟ chip area.