1 K. Tokonami, "Wave monitor for glitch detection and skew adjusting in high-speed DAC" 175-177, 2015
2 S. Piplani, "Test and Debug Strategy for High Speed JESD204B Rx PHY" 184-188, 2017
3 S. Huang, "An 8.2-to-10.3Gb/s Full-Rate Linear Reference-less CDR Without Frequency Detector in 0.18 μm CMOS" 152-153, 2014
4 R. Shivnaraine, "An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by"Phase Reset"" 61 : 2129-2138, 2014
5 P. K. Hanumolu, "A Wide-Tracking Range Clock and Data Recovery Circuit" 43 : 425-439, 2008
6 M. Chen, "A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology" 47 : 627-640, 2011
7 J. L. Sonntag, "A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links" 41 : 1867-1875, 2006
8 G. Shu, "A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous rate digital CDR with automatic frequency acquisition in 65nm CMOS" 150-151, 2014
9 C. Kromer, "A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects" 41 : 2921-2929, 2006
10 G. R. Gangasani, "A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology" 47 : 1828-1841, 2012
1 K. Tokonami, "Wave monitor for glitch detection and skew adjusting in high-speed DAC" 175-177, 2015
2 S. Piplani, "Test and Debug Strategy for High Speed JESD204B Rx PHY" 184-188, 2017
3 S. Huang, "An 8.2-to-10.3Gb/s Full-Rate Linear Reference-less CDR Without Frequency Detector in 0.18 μm CMOS" 152-153, 2014
4 R. Shivnaraine, "An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by"Phase Reset"" 61 : 2129-2138, 2014
5 P. K. Hanumolu, "A Wide-Tracking Range Clock and Data Recovery Circuit" 43 : 425-439, 2008
6 M. Chen, "A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology" 47 : 627-640, 2011
7 J. L. Sonntag, "A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links" 41 : 1867-1875, 2006
8 G. Shu, "A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous rate digital CDR with automatic frequency acquisition in 65nm CMOS" 150-151, 2014
9 C. Kromer, "A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects" 41 : 2921-2929, 2006
10 G. R. Gangasani, "A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology" 47 : 1828-1841, 2012
11 P. A. Francese, "A 16 Gb/s 3. 7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31kppm Tracking Bandwidth" 49 : 2490-2502, 2014
12 A. Kiaei, "A 10 Gb/s NRZ receiver with feedforward equalizer and glitch-free phasefrequency detector" 372-375, 2009
13 Wenjing Yin, "A 1. 6mW 1. 6ps-rms-jitter 2. 5GHz digital PLL with 0. 7-to-3. 5GHz frequency range in 90nm CMOS" 2010
14 H. Song, "A 1. 0-4. 0-Gb/s all-digital CDR with 1. 0-ps resolution DCO and adaptive proportional gain control" 46 : 424-434, 2010
15 A. Elshazly, "A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration" 46 (46): 2759-2771,
16 J. Jin, "A 0. 75-3. 0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR With a Deadzone-Compensated Frequency Detector" 53 : 2994-3003, 2018
17 Wenjing Yin, "8mW Highly Digital Phase-Locked Loop With Bandwidth Tracking" 46 (46): 1870-1880,
18 R. Bueren, "5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS" 166-169, 2008
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