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Hagyoul Bae,Sungchul Kim,Minkyung Bae,Ja Sun Shin,Dongsik Kong,Hyunkwang Jung,Jaeman Jang,Jieun Lee,Dae Hwan Kim,Dong Myong Kim IEEE 2011 IEEE electron device letters Vol.32 No.6
<P>Considering asymmetry caused by layout, process, and device degradation, separate extraction of the source and drain resistances, i.e., <I>RS</I> and <I>RD</I>, respectively, from the total resistance <I>R</I><SUB>TOT</SUB> is very important in the design, modeling, and characterization of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). Due to the insulated gate structure, however, separate extraction is difficult through direct-current <I>I</I>-<I>V</I> characterization. In this letter, we propose a simple and useful technique for separate extraction of <I>RS</I> from <I>RD</I> in a-IGZO TFTs through a two-terminal parallel-mode <I>C</I> -<I>V</I> technique. We experimentally verified the validity of the proposed technique by comparing the result with the source-to-drain resistance from the <I>I</I>-<I>V</I> characteristics.</P>