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Kim, Seong Kwang,Shim, Jae-Phil,Geum, Dae-Myeong,Kim, Jaewon,Kim, Chang Zoo,Kim, Han-Sung,Song, Jin Dong,Choi, Sung-Jin,Kim, Dae Hwan,Choi, Won Jun,Kim, Hyung-Jun,Kim, Dong Myong,Kim, Sanghyeon Institute of Electrical and Electronics Engineers 2018 IEEE transactions on electron devices Vol.65 No.5
<P>In this paper, we fabricated In<SUB>0.53</SUB>Ga<SUB>0.47</SUB>As-on insulator (OI) MOSFETs on Si substrates with different doping types to mimic ground plane doping using direct wafer bonding and epitaxial lift-off (ELO) techniques. We investigated the impact of doping types on the ground plane and the backgate biasing, which are important and preferable components in monolithic 3-D (M3D) integration, on the electrical properties of MOSFETs, such as the threshold voltage ( <TEX>${V} _{T}$</TEX>) and the effective mobility ( <TEX>$\mu _{\textsf {eff}}$</TEX>). It was found that <TEX>${V} _{T}$</TEX> and <TEX>$\mu _{\textsf {eff}}$</TEX> were significantly modulated by the backsubstrate doping and the backbiasing. These observations were explained by the change of carrier distributions, which were confirmed by technology computer-aided design simulation. Furthermore, we investigated the reusability of InP donor substrates for sequential epitaxial growth after ELO process toward a cost-effective M3D integration with the In<SUB>0.53</SUB>Ga<SUB>0.47</SUB>As channel.</P>
Kim, Seong Kwang,Shim, Jae-Phil,Geum, Dae-Myeong,Kim, Chang Zoo,Kim, Han-Sung,Song, Jin Dong,Choi, Sung-Jin,Kim, Dae Hwan,Choi, Won Jun,Kim, Hyung-Jun,Kim, Dong Myong,Kim, Sanghyeon Institute of Electrical and Electronics Engineers 2017 IEEE transactions on electron devices Vol.64 No.9
<P>Defect less semiconductor-on-insulator (-OI) by a cost-effective and low-temperature process is strongly needed for monolithic 3-D integration. Toward this, in this paper, we present a cost-effective fabrication of the indium gallium arsenide-OI structure featuring the direct wafer bonding (DWB) and epitaxial lift-off (ELO) techniques as well as the reuse of the indium phosphide donor wafer. We systematically investigated the effects of the prepatterning of the III-V layer before DWB and surface reforming (hydrophilic) to speed up the ELO process for a fast and high-throughput process, which is essential for cost reduction. Thismethod provides an excellent crystal quality of In0.53Ga0.47As on Si. Crystal quality of the film was evaluated using Raman spectra, and transmission electron microscope. Finally, we achieved good electrical properties of In0.53Ga0.47As-OImetal-oxide-semiconductorfield-effect-transistors fabricated through the proposed DWB and ELO.</P>
Low-Subthreshold-Slope Asymmetric Double-Gate GaAs-on-Insulator Field-Effect-Transistors on Si
Kim, SangHyeon,Geum, Dae-Myeong,Kim, Seong Kwang,Kim, Hyung-Jun,Song, Jin Dong,Choi, Won Jun IEEE 2016 IEEE electron device letters Vol.37 No.10
<P>In this letter, we have demonstrated low-subthreshold-slope (SS) asymmetric double-gate (DG) GaAs-on-insulator field-effect-transistors (FETs) on Si substrates via wafer bonding and epitaxial liftoff techniques. We found that DG FETs show lower SS than single-gate FETs all over the range of the drain current. A minimum value of SS was 68 mV/decade, which is very close to the theoretical limit. In addition, the achieved SS value was a record-low among the reported GaAs transistors so far.</P>