Hybrid Design For Testability Combining Scan and Clock Line Control and Method For Test Generation

Sanghyeon Baeg(백상현),William A. Rogers 대한전자공학회 1995 대한전자공학회 학술대회 Vol.1995 No.7

SRAM Interleaving Distance Selection With a Soft Error Failure Model

Sanghyeon Baeg,ShiJie Wen,Wong, R. IEEE 2009 IEEE transactions on nuclear science Vol.56 No.4

<P>The significance of multiple cell upsets (MCUs) is revealed by sharing the soft-error test results in three major technologies, 90 nm, 65 nm, and 45 nm. The effectiveness of single-bit error correction (SEC) codes can be maximized in mitigating MCU errors when used together with the interleaving structure in memory designs. The model proposed in this paper provides failure probability to probabilistically demonstrate the benefits of various interleaving scheme selections for the memories with SEC. Grouped events such as MCU are taken into account in the proposed model by using the compound Poisson process. As a result of the proposed model, designers can perform predictive analysis of their design choices of interleaving schemes. The model successfully showed the difference in failure probability for different choices of interleaving schemes. The model behaved as the upper bound for failure probability when compared to the neutron test data with the 45-nm static-random-access memory (SRAM) design.</P>

A <tex> $di/dt$</tex> Compensation Technique in Delay Testing by Disconnecting Power Pins

IEEE 2009 IEEE transactions on instrumentation and measureme Vol.58 No.10

<P>Scan-based delay testing increases power consumption, particularly peak power, due to excessive simultaneous signal switching. The instantaneous current changes increase the ground level during signal switching, slowing down the operational speed. When the switching activity increases during test operations, it is necessary to pay special attention to determine whether the speed failures are due to extra switching, since the blind application of delay testing can greatly affect the yield of a device. This paper demonstrates that cycle time adjustment is best suited to compensate for the timing issues resulting from the higher switching activity in delay testing. In the proposed method, the power pins are disconnected in an increasing number to find a proper level of cycle period adjustment. The power pins of a chip are experimentally disconnected to observe the ground bounce behavior, which is also demonstrated in simulations. The experimental results also demonstrate that the proposed method can avoid the problem of abandoning good devices by cycle adjustment.</P>

Quantification of Substrate Current Caused by an Individual Trap at Different Locations and Energies, Prevailing on Si/SiO2 Interface or Si Substrate of n-MOSFETs

Nosheen Shahzadi,Sanghyeon Baeg 대한전자공학회 2022 Journal of semiconductor technology and science Vol.22 No.4

Traps on Si/SiO2 interface or Si substrate are a big source of variability that cause the mismatch of transistors’ performance and leads to failure. To have a comprehensive view of individual traps, causing random fluctuations, variable trap locations are considered on Si/SiO2 interface and Si substrate. Each trap location is filled with a trap alternatively and simulated via Sentaurus TCAD at five different energy levels (0.35-0.55 eV with a difference of 0.05 eV). The electron charge pumping cycle is recorded to understand each trap's dynamics. In this study, electron charge emission in low time, contributing to substrate current is considered as an indicator to estimate degradation in device performance. The specific value of charge emission in low time contributing to substrate current from an individual-specified trap, reveals the impact of that trap on device degradation. A special case is also discussed to calculate the threshold of failure time based on the accumulation of one femtocoulomb charge in the low time.

Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress

Bae, Jongsun,Baeg, Sanghyeon,Park, Sungju IEEE 2012 IEEE transactions on instrumentation and measureme Vol.61 No.12

<P>The physical distance between adjacent memory cells is rapidly decreasing as memory density increases and technology geometry shrinks. As a result of the narrower distance, the capacitance between adjacent cells, which are referred to as the cell coupling capacitor (<TEX>$C_{\rm CCP}$</TEX>), increases and behaves as the source of crosstalk. The crosstalk is further aggravated by increasing operational speeds. When the sizes of the <TEX>$C_{\rm CCP}$</TEX> are marginal, they may not be detected by normal test patterns but can appear when various stresses accumulate. When they are not detected in an early manufacturing stage, they become the source of intermittent failures. Creating a complex test environment is sometimes rejected at the expense of higher parts per million of a device. In this paper, a negative voltage stress is applied to bit lines to test and diagnose the issues from the marginal <TEX>$C_{\rm CCP}$</TEX>. The negative voltage level is closely correlated to the <TEX>$C_{\rm CCP}$</TEX> size, which implies that the proposed method can be used as a vehicle to diagnose the potential issues due to cell coupling capacitors. The simulation results demonstrated that the negative stress voltage can screen the cell coupling capacitors from a few femtofarads to tens of femtofarads in an experimental circuit. The proposed technique has been validated by test chip using 130-nm technology.</P>

Signal characteristic and test exploitation for intermittent nanometer-scale cracks

Lee, Hosung,Baeg, Sanghyeon Elsevier 2018 Microelectronics reliability Vol.84 No.-

<P><B>Abstract</B></P> <P>This paper analyzes signal distortion caused by nanometer-scale solder ball fractures. A solder ball fracture causes an intermittent open circuit on the transmission line. The resulting basic failure mechanism is a drop in signal voltage, due to the capacitance-induced Alternating Current (AC)-coupling effect (which is induced by the fractured solder ball). The two major contributing factors to this error are fracture height and the persisting duration of the consecutive same-logic-value signal. The required signal that induces a voltage drop, sufficient to detect nanometer-scale solder ball fractures, can be composed by repetition of certain signal patterns even for the I/O connections with run-length restrictions. The methodology is newly proposed to determine potential ranges of solder ball fractures. Test pattern generation is made by maximally exploiting the compounding effect of various sizes of same data bits to generate effective run-length that is larger than maximum run length for the purpose of detecting intermittent solder ball fractures. In DDR3 memory systems with 5-nm solder ball fractures, at least 29 bits of consecutive logic “1” or “0” signals are required to detect fractures. If the system has a maximum run-length of 10, 20, or 30 bits, the test signal—which has the equivalent voltage-dropping effect as 29-consecutive bits—can be generated with six, two, or one repetition of the test pattern, respectively; the test pattern is in the form of concatenated N-1 bits of consecutive logic “1” and 1 bit of logic “0” where N is the maximum run length. In addition, a SPICE simulation was conducted to confirm correlation between calculations and actual results. In the simulation, in order to detect a 5-nm solder ball fracture, at least 37 bits of consecutive signal were required.</P> <P><B>Highlights</B></P> <P> <UL> <LI> The basic mechanism of the error by the nano-meter scale solder ball fracture </LI> <LI> The compounding effects of the switching signal for the fractured solder ball </LI> <LI> The methodology for selecting the target solder-ball-fracture range </LI> <LI> The methodology for generating the test pattern for the solder ball fracture </LI> </UL> </P>

Experimental Exploitation of Random and Deterministic Data Patterns for Stringent DDR4 I/O Timing Margins

Kiseok Lee,Tan Li,Sanghyeon Baeg 대한전자공학회 2019 Journal of semiconductor technology and science Vol.19 No.4

In this paper, I/O timing margins are experimentally measured by DQS groups, for a DDR4 RDIMM with 2133 Mbps data rate, to study the margin effects of the special combination and sequence of random and fault-based deterministic data patterns. The most effective 94 data patterns are newly developed after experimentally investigating three test patterns factors, which consist of test algorithms, address directions, and data patterns; the most influential factor was data patterns, which resulted in the average margin reduction of 15.2%. The maximum of 11.8% margin was reduced by the proposed 94 patterns (in comparison to 28-bit PRBS pattern), which was from both selected PRBS and fault-based deterministic data patterns.

Statistical distributions of row-hammering induced failures in DDR3 components

Park, Kyungbae,Yun, Donghyuk,Baeg, Sanghyeon Elsevier 2016 Microelectronics reliability Vol.67 No.-

<P>This work developed a statistical model of row hammering failures based on experimental results obtained with commodity DDR3 SDRAMs of 3 x nm technology. The statistical distribution for the failing rows with respect to the number of hamrnerings matched the normal distribution. The means mu(HAR) and standard deviations sigma(HMR) of the number of hammerings that cause row hammering failure were apparently different among three different manufacturers. The means of the manufacturers varied by more than 200% and could be sufficiently used to characterize the reliability of the device from a row hammering stress perspective. Based on the derived statistical model, the failed parts-per-million (ppm) was calculated to give, on average, 164.6, 82.6 and 22.2, respectively, for the manufacturers. (C) 2016 Elsevier Ltd. All rights reserved.</P>

Failure signature analysis of power-opens in DDR3 SDRAMs

Li, Tan,Lee, Hosung,Bak, Geunyong,Baeg, Sanghyeon Elsevier 2018 Microelectronics reliability Vol.88 No.-

<P><B>Abstract</B></P> <P>Open defects in power pins can only be diagnosed indirectly, and these diagnoses are a challenging task in failure analysis due to the failure signature's aliasing to other issues. Open defects cannot be detected by traditional DC-type test methods and can remain a potential risk in stressful device operation. In this work, error signatures in power open faults are experimentally probed to better understand electrical signatures induced by power-open. The power open faults are intentionally injected into a DDR3 SDRAM test platform. The power network inside the DDR3 SDRAM is experimentally found to be asymmetrical. Power-open defects in one power pin produce a range of power noise (0–65 mV), depending on the location of the power pin.</P> <P><B>Highlights</B></P> <P> <UL> <LI> Power open faults are intentionally injected into customized DDR3 SDRAM test platform. </LI> <LI> Error signatures in power open faults are experimentally probed. </LI> <LI> The power network inside the DDR3 SDRAM is experimentally found to be asymmetrical. </LI> <LI> Power-open defects of one power ball increased power noise for a DDR3 component. </LI> </UL> </P>

Stuck Bits Study in DDR3 SDRAMs Using 45-MeV Proton Beam

Chulseung Lim,Hyun Soo Jeong,Geunyong Bak,Sanghyeon Baeg,Shi-Jie Wen,Wong, Richard Professional Technical Group on Nuclear Science 2015 IEEE transactions on nuclear science Vol.62 No.2

<P>This work shares the observations of stuck bits by proton beam in DDR3 components in 3x-nm technologies. The DDR3 SDRAMs from four major DRAM manufacturers were tested with a 45-MeV proton beam at an operating frequency of 800 MHz. The beam exposure resulted in single bit upset (SBU) and multiple bit upsets (MBUs), as well as single and multiple stuck bits in a word due to micro-dose and displacement damage effects. The number of stuck bits reduced as the refresh interval duration was decreased. Moreover, for the tested samples, the stuck bits were recovered completely and could be run in the normal operation mode after annealing at 150<SUP>°</SUP>C. The occurrence of multiple stuck bits in a word was likely due to damages to the control logic and those stuck bits were recovered as well after annealing at 150<SUP>°</SUP>C.</P>