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ByungcheulKim,Sang-BaeYi,Kwang-YellSeo 한국물리학회 2002 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.41 No.6
A scaled polysilicon-oxide-nitride-oxide-silicon (SONOS) single-transistor memory cell in a NOR structure with common source lines is proposed for high density, and its operating conditions are demonstrated. The cell area of the SONOS single-transistor memory realized by using 0.35-$\mu$m complementary metal-oxide-semiconductor (CMOS) technology is 1.32 $\mu$m$^2$. A selected cell is programmed by applying 3 V to the gate and $-$5.5 V to the source, drain, and substrate, and is erased by applying $-$5.5 V to the gate and 3 V to the source, drain, and substrate. Drain disturbance is inhibited by applying $-$5.5 V to the gate of an unselected cell sharing the bit-line. Gate program-inhibit is achieved only within the limit of 50 ms of programming time at pre-cycle by applying 0 V to the drain of an unselected cell sharing the word-line. These make it possible to operate from 3-V single power supply.