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Ritesh Gupta,Sandeep Kr Aggarwal,Mridula Gupta,R. S. Gupta 대한전자공학회 2006 Journal of semiconductor technology and science Vol.6 No.3
A new analytical model has been proposed for predicting the sheet carrier density of Metal insulator Semiconductor High Electron Mobility Transistor (MISHEMT). The model takes into account the non-linear relationship between sheet carrier density and quasi Fermi energy level to consider the quantum effects and to validate it from subthreshold region to high conduction region. Then model has been formulated in such a way that it is applicable to MESFET/HEMT/MISFET with few adjustable parameters. The model can also be used to evaluate the characteristics for different gate insulator geometries like T-gate etc. The model has been extended to forecast the drain current, conductance and high frequency performance. The results so obtained from the analysis show excellent agreement with previous models and simulated results that proves the validity of our model.
Gupta, Ritesh,Aggarwal, Sandeep Kr,Gupta, Mridula,Gupta, R.S. The Institute of Electronics and Information Engin 2006 Journal of semiconductor technology and science Vol.6 No.3
A new analytical model has been proposed for predicting the sheet carrier density of Metal insulator Semiconductor High Electron Mobility Transistor (MISHEMT). The model takes into account the non-linear relationship between sheet carrier density and quasi Fermi energy level to consider the quantum effects and to validate it from subthreshold region to high conduction region. Then model has been formulated in such a way that it is applicable to MESFET/HEMT/MISFET with few adjustable parameters. The model can also be used to evaluate the characteristics for different gate insulator geometries like T-gate etc. The model has been extended to forecast the drain current, conductance and high frequency performance. The results so obtained from the analysis show excellent agreement with previous models and simulated results that proves the validity of our model.
Gupta, Ritesh,Kaur, Ravneet,Aggarwal, Sandeep Kr,Gupta, Mridula,Gupta, R.S. The Institute of Electronics and Information Engin 2010 Journal of semiconductor technology and science Vol.10 No.1
Improvement in breakdown voltage ($BV_{ds}$) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length ($L_g$), but due to lithographic limitation, shortening $L_g$ below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the $BV_{ds}$ of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in $BV_{ds}$ can be obtained by applying field plates, especially at the drain side. The important parameters affecting $BV_{ds}$ and cut-off frequency ($f_T$) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, $\Gamma$-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.
Ritesh Gupta,Ravneet Kaur,Sandeep Kr Aggarwal,Mridula Gupta,R. S. Gupta 대한전자공학회 2010 Journal of semiconductor technology and science Vol.10 No.1
Improvement in breakdown voltage (BVds) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length (Lg), but due to lithographic limitation, shortening Lg below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate on to the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the BVds of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in BVds can be obtained by applying field plates, especially at the drain side. The important parameters affecting BVds and cut-off frequency (fT) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, Γ-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.