http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
- 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
- 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
RISS 인기검색어
- 검색키워드
- 저자 : Qingsheng HU (검색결과 2 건)
- 무료
- 기관 내 무료
- 유료
-
A 10 Gb/s Equalizer in 0.18m CMOS Technology for High-speed SerDes
Mingke Zhang,Qingsheng Hu 보안공학연구지원센터 2014 International Journal of Control and Automation Vol.7 No.11
A 10 Gb/s equalizer consisting of analog equalizer and two-tap half-rate decision feedback equalizer (DFE) in 0.18m CMOS has been designer. By employing capacitive degeneration and inductive peaking techniques, the analog equalizer achieves large boosting. The pipelined half-rate architecture is used to improve the transmitted data rate in DFE with a small increase in area. Measurement results show that the distorted signal is well recovered by this equalizer and consumes 27 mW with the supply voltage of 1.8-V. The overall chip area including pads is 0.60.7 mm2.
-
A Fair Scheduling Algorithm for Input-Queued Switches
Hua-An ZHAO,Qingsheng HU 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
To increase both the capacity and the processing speed for input-queued (IQ) switches, we proposed a fair scalable scheduling architecture (FSSA) where several chips of cascaded sub-scheduler compose a large-scale high performance network scheduler. In this paper, we present an improved scheduling algorithm named DIFSSA where a distributed iteration scheme is employed based on FSSA. The simulation and measurement results show that DIFSSA achieves better performance on average delay and throughput under heavy loads compared to existing algorithms and its scheduler performance and the processing time are also better than the other. Moreover, it has been implemented by 4 Xilinx FPGAs as 64×64 switch whose data rates can be up to 800Mbps and the tradeoff between performance and hardware complexity has been solved peacefully.
연관 검색어 추천
이 검색어로 많이 본 자료
활용도 높은 자료
