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- 검색키워드
- 저자 : Pritam Bhattacharjee (검색결과 2 건)
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LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications
Pritam Bhattacharjee,Bipasha Nath,Alak Majumder 대한전자공학회 2017 대한전자공학회 학술대회 Vol.2017 No.1
Power dissipation in integrated circuits is one of the major concerns to the research community, at the verge when more number of transistors are integrated on a single chip. The substantial source of power dissipation in sequential elements of the integrated circuit is due to the fast switching of high frequency clock signals. These signals do not carry any information and are mainly intended to synchronize the operation of sequential components. This unnecessary switching of Clock, during the HOLD phase of either ‘logic 1’ or ‘logic 0’, may be eliminated using a technique, called Clock Gating. In this paper, we have incorporated a recent clock gating style called LECTOR–based clock gating (LB–CG) to drive multi–stage architecture and simulated its performance using 90nm CMOS Predictive Technology Model (PTM) with a power supply of 1.1V at 18GHz clock frequency. A substantial savings in terms of average power in comparison to its non–gated correspondent have been observed.
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A 23.52μW / 0.7V Multi-stage Flip-flop Architecture Steered by a LECTOR-based Gated Clock
Pritam Bhattacharjee,Alak Majumder,Bipasha Nath 대한전자공학회 2017 IEIE Transactions on Smart Processing & Computing Vol.6 No.3
Technology development is leading to the invention of more sophisticated electronics appliances that require long battery life. Therefore, saving power is a major concern in current-day scenarios. A notable source of power dissipation in sequential structures of integrated circuits is due to the continuous switching of high-frequency clock signals, which do not carry any information, and hence, their switching is eliminated by a method called clock gating. In this paper, we have incorporated a recent clock-gating style named Leakage Control Transistor (LECTOR)-based clock gating to drive a multi-stage sequential architectures, and we focus on its performance under three different process corners (fast-fast, slow-slow, typical-typical) through Monte Carlo simulation at 18 ㎓ clock with 90 ㎚ technology. This gating is found to be one of the best gated approaches for multi-stage architectures in terms of total power consumption.
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