LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications

다국어 초록 (Multilingual Abstract)

Power dissipation in integrated circuits is one of the major concerns to the research community, at the verge when more number of transistors are integrated on a single chip. The substantial source of power dissipation in sequential elements of the integrated circuit is due to the fast switching of high frequency clock signals. These signals do not carry any information and are mainly intended to synchronize the operation of sequential components. This unnecessary switching of Clock, during the HOLD phase of either ‘logic 1’ or ‘logic 0’, may be eliminated using a technique, called Clock Gating. In this paper, we have incorporated a recent clock gating style called LECTOR–based clock gating (LB–CG) to drive multi–stage architecture and simulated its performance using 90nm CMOS Predictive Technology Model (PTM) with a power supply of 1.1V at 18GHz clock frequency. A substantial savings in terms of average power in comparison to its non–gated correspondent have been observed.

목차 (Table of Contents)

• Abstract
• 1. Introduction
• 2. Brief Survey on Clock Gating
• 3. Circuit incorporating Multi-Stage Operation
• 4. Simulation Result & Analysis
• 5. Conclusion
• References