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- 저자 : Paul P. Conway (검색결과 1 건)
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ZhiYong Wu,Zhiheng Huang,Yucheng Ma,Hua Xiong,Paul P. Conway 대한금속·재료학회 2014 ELECTRONIC MATERIALS LETTERS Vol.10 No.1
Through-silicon vias (TSVs) have been investigated extensively in recent years. However, the physical mechanisms behind some of the common problems associated with TSVs, such as the protrusion of Cu vias, are still unknown. In addition, since the dimensions of TSVs have been shrunk to microscopic levels, the sizes of the microstructural features of TSVs are no longer small compared to the dimensions of the vias. Therefore, the role and importance of the microstructural features of TSVs need to be studied to enable more accurate reliability predictions. This study focused on the effects the microstructural features of TSVs, i.e., the Cu grains and their [111] texture, grain size distribution, and morphology, have on the thermally induced linear elastic behavior of the vias. The results of the study indicate that stress distribution in the model that takes into account the Cu grains, whose Young’s moduli and Poisson’s ratios are set according to their crystallographic orientations, is more heterogeneous than that in a reference model in which the bulk properties of Cu are used. Stresses as high as 250 MPa are observed in the via of the model that takes into consideration the Cu grains, while stresses in the via of the reference model are all lower than 150 MPa. In addition, smaller Cu grains in the vias result in higher stresses; however, the variation in stress owning to changes in the grain size is within 20 MPa. The frequency of the stresses ranging from 80 MPa to 100 MPa was the highest in the stress distribution of the vias, depending on boundary conditions. The stress level in the vias decreases with the decrease in the number of grains with the [111] texture. Finally, the stress level is lower in the model in which the grain structure is generated using a phase field model and is closer to that of the microstructures present in real materials.
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