http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
- 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
- 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
RISS 인기검색어
- 검색키워드
- 저자 : Nogueira Gabriel Leonardo (검색결과 2 건)
- 무료
- 기관 내 무료
- 유료
-
Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation
Gabriel Leonardo Nogueira,Maiza da Silva Ozório,Marcelo Marques da Silva,Rogério Miranda Morais,Neri Alves 대한금속·재료학회 2018 ELECTRONIC MATERIALS LETTERS Vol.14 No.3
We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation ofa tin (Sn) layer. Bare aluminum oxide (Al2O3), obtained by anodization, and Al2O3covered with a polymethylmethacrylate(PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carriedout to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openingsthat give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable foruse in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare Al2O3. The addition of a PMMA layer on the Al2O3surface modifies the morphology of the Sn layer, resulting in a lowering of thethreshold voltage. The values of threshold voltage and electric field, VTH= − 8 V and ETH= 354.5 MV/m respectively, werecalculated using an Al2O3film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare Al2O3thesevalues were VTH= − 10 V and ETH= 500 MV/m.
-
Vieira Douglas Henrique,Nogueira Gabriel Leonardo,Nascimento Mayk Rodrigues,Fugikawa-Santos Lucas,Alves Neri 한국물리학회 2023 Current Applied Physics Vol.53 No.-
Charge-trap memory phenomena were demonstrated in an electrolyte-gated transistor (EGT) using a spray-coated zinc oxide (ZnO) active layer and a cellulose-based electrolyte. The EGT exhibited efficient programming and erasing characteristics at low voltages, shifting the threshold voltage and the magnitude of the on-current. This behavior is discussed in terms of the influence of charged trapping states at the ZnO/electrolyte interface and within the ZnO bulk. The presence of these traps leads to a shift in the mobility from 0.57 ± 0.16 cm2 V-1 s-1 in the initial state to 0.02 ± 0.01 cm2 V-1 s-1 when programmed. Retention experiments revealed improved stability of the memory state when a low positive voltage is applied to the gate, indicating that the device’s characteristics are extremely sensitive to the trapping/detrapping of charges at the semiconductor/ electrolyte interface. Capacitance spectroscopy measurements using planar and metal-insulator-semiconductor configurations within the same device were used to analyze the charging dynamics of the trap states at different programming states.
연관 검색어 추천
이 검색어로 많이 본 자료
활용도 높은 자료
