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- 저자 : Rogério Miranda Morais (검색결과 1 건)
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Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation
Gabriel Leonardo Nogueira,Maiza da Silva Ozório,Marcelo Marques da Silva,Rogério Miranda Morais,Neri Alves 대한금속·재료학회 2018 ELECTRONIC MATERIALS LETTERS Vol.14 No.3
We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation ofa tin (Sn) layer. Bare aluminum oxide (Al2O3), obtained by anodization, and Al2O3covered with a polymethylmethacrylate(PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carriedout to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openingsthat give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable foruse in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare Al2O3. The addition of a PMMA layer on the Al2O3surface modifies the morphology of the Sn layer, resulting in a lowering of thethreshold voltage. The values of threshold voltage and electric field, VTH= − 8 V and ETH= 354.5 MV/m respectively, werecalculated using an Al2O3film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare Al2O3thesevalues were VTH= − 10 V and ETH= 500 MV/m.
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