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Prashant Kumar,Neeraj Gupta,Nitin Sachdeva,Tarun Sachdeva,Munish Vashishath 대한전자공학회 2020 Journal of semiconductor technology and science Vol.20 No.3
The rapidly growth in semiconductor industry puts huge demand of scalable devices with low standby power for future VLSI chips. The further mitigation in device dimension becomes a challenging task due to the existence of unavoidable short channel effects. The introduction of gate stack and channel engineering in MOSFET devices open a new window for future generation devices. This paper presents gate stack structure with low-κ dielectric material as silicon oxide and replacement of various high-κ dielectric materials to analyze the device performance. The unification of new oxide material in the device enhances the immunity against SCEs and improves the gate leakage current. Dual-Halo Dual-Dielectric Triple Material Surrounding Gate (DH-DD-TM-SG) MOSFET has shown better performance with high dielectric constant materials. The device exhibits more value of transconductance with high-κ dielectrics.