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ASIP Instructions and Their Hardware Architecture for H.264 / AVC
Jung H. Lee,Sung D. Kim,Myung H. Sunwoo 대한전자공학회 2005 Journal of semiconductor technology and science Vol.5 No.4
H.264/AVC adopts new features compared with previous multimedia algorithms. It is inefficient to implement some of the new blocks using existing DSP instructions. Hence, new instructions are required to implement H.264/AVC. This paper proposes novel instructions for intra-prediction, in-loop deblocking filter, entropy coding and integer transform. Performance comparisons show that the required computation cycles for the in-loop deblocking filter can be reduced about 20 ~ 25%. This paper also proposes new instructions for the integer transform. The proposed instructions can execute one dimension forward/inverse integer transform. The integer transform can be implemented using much smaller hardware size than existing DSPs.
ASIP Instructions and Their Hardware Architecture for H.264/AVC
Lee, Jung-H.,Kim, Sung-D.,Sunwoo, Myung-H. The Institute of Electronics and Information Engin 2005 Journal of semiconductor technology and science Vol.5 No.4
H.264/AVC adopts new features compared with previous multimedia algorithms. It is inefficient to implement some of the new blocks using existing DSP instructions. Hence, new instructions are required to implement H.264/AVC. This paper proposes novel instructions for intra-prediction, in-loop deblocking filter, entropy coding and integer transform. Performance comparisons show that the required computation cycles for the in-loop deblocking filter can be reduced about $20{\sim}25%$. This paper also proposes new instructions for the integer transform. The proposed instructions can execute one dimension forward/inverse integer transform. The integer transform can be implemented using much smaller hardware size than existing DSPs.
Design and Implementation of a General Purpose Parallel Image Processor Chip
Sunwoo,Myung H.,Ong,Soo Hwan,Ahn,Byung Dug,Lee,Kyung Woo 대한전자공학회 1995 ICVC : International Conference on VLSI and CAD Vol.4 No.1
This paper presents the design and implementation of a general purpose parallel image processor chip called the Sliding Memory Plane (SIiM) Image Processor to build a meshconnected SIMD architecture called the SIiM Array Processor. The SIiM Image Processor chip consists of 5 × 5 processing elements (PEs) connected by a mesh topology. Due to the idea of sliding, that is, overlapping inter-PE communication with computation, the SIiM Image Processor can greatly reduce the inter-PE communication overhead, a significant disadvantage of existing array processors. This paper addresses architectures of the SIiM Image Processor chip, the design of an instruction set, and implementation issues. The chip has 55,255 gates and twenty five 128 × 9-bit SRAM modules, was simulated at 18 MHz for the worst-case conditions, and actually run at a higher clock rate. The die size is 382.69 × 370.44 mil and the package type is the 144 pin MQFP. We have conducted the performance evaluation of the chip that shows a significant improvement.
Bit Manipulation Accelerator for Communication Systems Digital Signal Processor
Jeong, Sug H.,Sunwoo, Myung H.,Oh, Seong K. Hindawi Publishing Corporation 2005 EURASIP journal on applied signal processing Vol.2005 No.16
<P>This paper proposes application-specific instructions and their bit manipulation unit (BMU), which efficiently support scrambling, convolutional encoding, puncturing, interleaving, and bit stream multiplexing. The proposed DSP employs the BMU supporting parallel shift and XOR (exclusive-OR) operations and bit insertion/extraction operations on multiple data. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18 μm standard cell library and the gate count of the BMU is only about 1700 gates. Performance comparisons show that the number of clock cycles can be reduced about 40%∼80% for scrambling, convolutional encoding, and interleaving compared with existing DSPs.</P>
Reconfigurable Hardware Structures for Spreading and Scrambling Operations
Jeong, Sug H.,Sunwoo, Myung H.,Oh, Seong K. The Institute of Electronics and Information Engin 2003 Journal of semiconductor technology and science Vol.3 No.4
This paper proposes reconfigurable hardware structures for spreading and scrambling of multi-mode CDMA systems. The proposed reconfigurable structures supporting IS-95, cdma2000 and WCDMA, include a pseudo noise code generator, a channelization code generator and a control circuit for signal flow control. The proposed reconfigurable structures provide an efficient hardware usage for multi-mode CDMA systems. The synthesis results show the area reduction about 24.7% compared with the original code generators. The proposed structures can provide efficient reconfigurability and high speed operations for future SDR systems.