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A Design of Vernier Coarse-Fine Time-to-Digital Converter using Single Time Amplifier
Jongsuk Lee,Yong Moon 대한전자공학회 2012 Journal of semiconductor technology and science Vol.12 No.4
A Coarse-Fine Time-to-Digital Converter (TDC) using the single time amplifier is proposed. A vernier delay line is used to overcome process dependency and the 2-stage time amplifier is designed to have high resolution by increasing the gain of the time amplifier. Single time amplifier architecture reduces the silicon area of the TDC and alleviates mismatch effect between time amplifiers. The proposed TDC is implemented in 0.18 ㎛ CMOS process with the supply voltage of 1.8 V. The measured results show that the resolution of the TDC is 0.73 ㎰ with 10-bit digital output, although highend process is not applied. The single time amplifier architecture reduces 13% of chip area compared to previous work. By reducing the supply voltage, the linearity of the TDC is enhanced and the resolution is decreased to 1.45 ㎰.
A stable U-band VCO in 65 nm CMOS with -0.11 dBm high output power
Jongsuk Lee,Yong Moon 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.4
A high output power voltage controlled oscillator (VCO) in the U-band was implemented using a 65 nm CMOS process. The proposed VCO used a transmission line to increase output voltage swing and overcome the limitations of CMOS technologies. Two varactor banks were used for fine tuning with a 5% frequency tuning range. The proposed VCO showed small variation in output voltage and operated at 51.55-54.18 GHz. The measured phase noises were -51.53 dBc/Hz, -91.84 dBc/Hz, and -101.07 dBc/Hz at offset frequencies of 10 kHz, 1 MHz, and 10 MHz, respectively, with stable output power. The chip area, including the output buffer, is 0.16×0.16 ㎟ and the maximum output power was -0.11 dBm. The power consumption was 33.4 mW with a supply voltage of 1.2-V. The measured FOMP was -190.8 dBc/Hz.
The Design of a 0.15 ps High Resolution Time-to-Digital Converter
Jongsuk Lee,Yong Moon 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.3
This research outlines the design of a HRTDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a 0.18 μm CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2SVTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.
A Design of 8.5 GHz META-VCO based-on Meta-material using 65 nm CMOS Process
Jongsuk Lee,Yong Moon 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.5
A low phase noise META-VCO based-on meta-structure was designed using 65 nm CMOS process. We used a meta-structure to get good phase noise characteristics. The measured phase noises are - 67.8 dBc/Hz, -96.37 dBc/Hz, and -107.37 dBc/Hz at 100 kHz, 1 MHz, and 10 MHz offset respectively. The META-VCO operates 8.45~8.77 GHz according to VCTRL, and the output power is -19.12 dBm. The power consumption is 28 mW with 1.2-V supply voltage. The calculated FOM is -140.76 dBc/Hz.
A Design of Vernier Coarse-Fine Time-to-Digital Converter using Single Time Amplifier
Lee, Jongsuk,Moon, Yong The Institute of Electronics and Information Engin 2012 Journal of semiconductor technology and science Vol.12 No.4
A Coarse-Fine Time-to-Digital Converter (TDC) using the single time amplifier is proposed. A vernier delay line is used to overcome process dependency and the 2-stage time amplifier is designed to have high resolution by increasing the gain of the time amplifier. Single time amplifier architecture reduces the silicon area of the TDC and alleviates mismatch effect between time amplifiers. The proposed TDC is implemented in $0.18{\mu}m$ CMOS process with the supply voltage of 1.8 V. The measured results show that the resolution of the TDC is 0.73 ps with 10-bit digital output, although highend process is not applied. The single time amplifier architecture reduces 13% of chip area compared to previous work. By reducing the supply voltage, the linearity of the TDC is enhanced and the resolution is decreased to 1.45 ps.
A Design of 8.5 GHz META-VCO based-on Meta-material using 65 nm CMOS Process
Lee, Jongsuk,Moon, Yong The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.5
A low phase noise META-VCO based-on meta-structure was designed using 65 nm CMOS process. We used a meta-structure to get good phase noise characteristics. The measured phase noises are -67.8 dBc/Hz, -96.37 dBc/Hz, and -107.37 dBc/Hz at 100 kHz, 1 MHz, and 10 MHz offset respectively. The META-VCO operates 8.45~8.77 GHz according to VCTRL, and the output power is -19.12 dBm. The power consumption is 28 mW with 1.2-V supply voltage. The calculated FOM is -140.76 dBc/Hz.
The Design of a 0.15 ps High Resolution Time-to-Digital Converter
Lee, Jongsuk,Moon, Yong The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.3
This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a $0.18{\mu}m$ CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.
Lee, Chung,Bae, Joon S.,Ryu, Gyu H.,Kim, Nayoung K.D.,Park, Donghyun,Chung, Jongsuk,Kyung, Sungkyu,Joung, Je-Gun,Shin, Hyun-Tae,Shin, Seung-Ho,Kim, Younglan,Kim, Byung S.,Lee, Hojun,Kim, Kyoung-Mee,Ki Elsevier 2017 The Journal of molecular diagnostics Vol.19 No.5
<P>Customized gene-panel tests, based on next-generation sequencing, have demonstrated their usefulness in a plethora of clinical settings. As with other clinical diagnostic techniques, gene-panel sequencing for clinical purposes requires precise quality control (QC) measures to ensure its reliability. Only detected variants are currently recorded in clinical reports; however, identifying whether a nondetected variant is a true or false negative is regarded essential in a clinical setting and, thus, a comprehensive QC measure is in demand. Conventional QC metrics, such as mean coverage and uniformity, are considered inadequate for such an evaluation. As such, a more specific measure focused on clinically important variants is herein proposed. In this study, we suggest a new scoring method for assessing the quality of clinical gene-panel sequencing data, specifically for the detection of a set of single-nucleotide variants. The performance of the method was analyzed using 2295 clinical samples (1012 formalin-fixed, paraffin-embedded and 1283 fresh-frozen tissues), and was shown to provide additional information that conventional methods do not show, such as mean depth and uniformity. Customized sequencing protocols, which include QC criteria, have been optimized by each genomic laboratory. The pass rate scoring method proposed in this study provides an appropriate QC response variable for the customized panel, which strengthens the reliability of calls on clinically relevant variants implicated in clinical reports.</P>
A stable U-band VCO in 65 nm CMOS with -0.11 dBm high output power
Lee, Jongsuk,Moon, Yong The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.4
A high output power voltage controlled oscillator (VCO) in the U-band was implemented using a 65 nm CMOS process. The proposed VCO used a transmission line to increase output voltage swing and overcome the limitations of CMOS technologies. Two varactor banks were used for fine tuning with a 5% frequency tuning range. The proposed VCO showed small variation in output voltage and operated at 51.55-54.18 GHz. The measured phase noises were -51.53 dBc/Hz, -91.84 dBc/Hz, and -101.07 dBc/Hz at offset frequencies of 10 kHz, 1 MHz, and 10 MHz, respectively, with stable output power. The chip area, including the output buffer, is $0.16{\times}0.16mm^2$ and the maximum output power was -0.11 dBm. The power consumption was 33.4 mW with a supply voltage of 1.2-V. The measured $FOM_P$ was -190.8 dBc/Hz.