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Virtual ground monitoring for high fault coverage of linear analog circuits
Roh, Jeongjin The Institute of Electronics and Information Engin 2002 Journal of semiconductor technology and science Vol.2 No.3
This paper explains a technique to improve the fault coverage of oscillation-test [1-5] for linear analog circuits. The transient behavior of the virtual ground is monitored during oscillation to extract information of the circuit. The limitation of the oscillation-test is analyzed, and an efficient signature analysis technique is proposed to maximize the fault coverage. The experimental result proves that the parametric fault coverage can be significantly increased by the proposed technique.
A 0.6-V Delta–Sigma Modulator With Subthreshold-Leakage Suppression Switches
Hyungdong Roh,Hyoungjoong Kim,Youngkil Choi,Jeongjin Roh,Yi-Gyeong Kim,Jong-Kee Kwon IEEE 2009 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.56 No.11
<P>A 0.6-V 34-mu W delta-sigma modulator implemented by using a standard 0.13-mu m complementary metal-oxide-semiconductor technology is presented. This brief analyzes a subthreshold-leakage current problem in switched-capacitor circuits and proposes subthreshold-leakage suppression switches to solve the problem. To verify the operation of the subthreshold-leakage suppression switches, two different fifth-order delta-sigma modulators are implemented with conventional switches and new switches. The input feedforward architecture is used to reduce the voltage swings of the integrators. A high-performance low-quiescent amplifier architecture is developed for the modulator. The modulator, with new switches, achieves a dynamic range of 83 dB, a peak signal-to-noise ratio of 82 dB, and a peak signal-to-noise-plus-distortion ratio of 81 dB in a signal bandwidth of 20 kHz. The power consumption is 34 mu W for the modulator, and the core chip size is 0.33 mm(2).</P>
Design of Digital Decimation Filter for Delta-Sigma A/D Converters
Hyungdong Roh,Sanho Byun,Seongyoung Ryu,Youngkil Choi,Hyunseok Nam,Jeongjin Roh 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
This paper presents details of the design and implementation of a fully synthesized digital decimation filter that provides time-to-market advantage for delta-sigma analog-todigital converters. This decimation filter is fabricated in 0.25-㎛ CMOS technology with 1.36 ㎡ of active area, and shows 4.4 ㎽ power consumption at a clock rate of 2.8224 ㎒. Experimental results show that this digital decimation filter is suitable for oversampled data converters and can be ported to new processes with fast redesign time since it does not have processdependent ROM or RAM circuits.
혼성 신호에 대한 시간 및 주파수 영역에서의 시그니처 분석 방법
노정진 漢陽大學校 工學技術硏究所 2002 工學技術論文集 Vol.11 No.-
본 논문에서는 혼성 신호 회로에서 파라메트릭 결점을 찾기 위한 새로운 긱술을 제안하였다. 본 논문에서는 기존의 혼성신호 회로에서 많이 사용되는 정현파 신호 대신 다양한 주파수 성분을 가지는 Linear Feedback Shift Register (LFSR)에서 발생된 디지털 랜덤 신호를 입력으로서 사용하는 방법을 제시한다. LFSR에서 발생된 신호는 테스트 회로로 입력되고, 그 출력신호는 웨이블렛 기법을 사용하여 각 주파수영역으로 분석된다. 각 주파수 대역에서의 시그니처 (Signature) 발생은 디지털 적분기를 사용하였다. LFSR에서 발생된 신호는 그 특성상 주파수 성분이 전 대역에 존재하는 화이트 노이즈와 유사하다. 따라서 이러한 특성을 활용하여 웨이블렛의 입력 신호로서 사용함으로서 혼성신호 회로에서의 테스트 성능을 향상시킬 수 있다. Pseudo-random sequence from linear feedback shift register(LFSR) is fed to circuit undertest(CUT) as stimulus. Wavelets are used to compact the transient response under this stimulus into a small number of signature. Wavelet based scheme decomposes the transient response into a number of signal in different frequency bands. Each decomposed signal is compacted into a signature using digital integrator. The digtal pulses from LFSR, owing to its pseudo-randomness property, are almost uniform in frequency domain, which generates multifrequency response when passed through CUT. This kind of transient response is well-suited for wavelet based signature analyzer since it decomeposes the response into several frequency bands.
Duan, Quanzhen,Roh, Jeongjin IEEE 2015 IEEE Transactions on Circuits and Systems I: Regul Vol.62 No.3
<P>This study presents a high-precision CMOS bandgap reference (BGR) circuit with low supply voltage. The proposed BGR circuit consists of two BGR cores and a curvature correction circuit, which includes a current mirror and a summing circuit. Two BGR cores adopt conventional structures with the curvature-down characteristics. A current-mirror circuit is proposed to implement one of the BGR cores to have the curvature-up characteristic. Selection of the appropriate resistances in the BGR cores results in one reference voltage with a well balanced curvature-down characteristic and another reference voltage with an evenly balanced curvature-up characteristic. The summation of these reference voltages is proposed to achieve a high-order curvature compensation. This curvature correction circuit causes the proposed BGR circuit without any trimming to show a measured temperature coefficient (TC) as low as 4.2 <TEX>$\hbox{ppm}/^{\circ}\hbox{C}$</TEX> over a wide temperature range of 160 <TEX>$^{\circ}\hbox{C}$</TEX> <TEX>$(-\hbox{40}\sim \hbox{120}~^{\circ}\hbox{C})$</TEX> at a power supply voltage of 1.2 V. The average TC for 8 random samples is approximately 9.3 <TEX>$\hbox{ppm}/^{\circ}\hbox{C}$</TEX> . The measured power-supply rejection ratio (PSRR) of <TEX>$-$</TEX>30 dB is achieved at the frequency of 100 kHz. The total chip size is 0.063 <TEX>${\rm mm}^{2}$</TEX> with a standard 0.13-<TEX>$\mu{\rm m}$</TEX> CMOS process.</P>
Recent Developments in High Resolution Delta-Sigma Converters
Kim, Jaedo,Roh, Jeongjin The Institute of Semiconductor Engineers 2021 Journal of semiconductor engineering Vol.2 No.1
This review paper describes the overall operating principle of a discrete-time delta-sigma modulator (DTDSM) and a continuous-time delta-sigma modulator (CTDSM) using a switched-capacitor (SC). In addition, research that has solved the problems related to each delta-sigma modulator (DSM) is introduced, and the latest developments are explained. This paper describes the chopper-stabilization technique that mitigates flicker noise, which is crucial for the DSM. In the case of DTDSM, this paper addresses the problems that arise when using SC circuits and explains the importance of the operational transconductance amplifier performance of the first integrator of the DSM. In the case of CTDSM, research that has reduced power consumption, and addresses the problems of clock jitter and excess loop delay is described. The recent developments of the analog front end, which have become important due to the increasing use of wireless sensors, is also described. In addition, this paper presents the advantages and disadvantages of the three-opamp instrumentation amplifier (IA), current feedback IA (CFIA), resistive feedback IA, and capacitively coupled IA (CCIA) methods for implementing instrumentation amplifiers in AFEs.
Common Mode Feedback 회로를 사용한 Fully Differential Operational Amplifier의 비교 및 분석
정근정,노정진 漢陽大學校 工學技術硏究所 2002 工學技術論文集 Vol.11 No.-
아날로그 IC의 signal swing을 증가시키고 노이즈를 감소시키는 기본적인 방법들 중에 한가지가 fully-differential 회로를 이용하는 것이다. 하지만, differential-mode signal processing에 영향을 미치는 DC 출력 level을 안정되도록 하기 위해서는 common-mode feedback (CMFB)회로가 사용되어져야 한다. 본 논문에서는 CMFB를 구성하는 방법을 기술한다. 또한, 출력 level를 안정되도록 하기 위해 사용되어지는 error amplifier들을 비교해 보고, error amplifier를 제안한다. 제안된 error amplifier 는 phase margin 증가 및 입력이 swing 할 수 있는 폭을 증가시킨다. One of the standard techniques to increase the signal swing and reduce noise is to use fully-differential circuits. However, the common-mode feedback(CMFB) loops that are used to stabilize the DC output level also affect the differential-mode processing. In this paper, a general description is given to fully-differential amplifiers with their CMFB loops, and compare the error amplifiers, then new error amplifiers that stabilize the DC output level is proposed. We designed a simple and efficient bias circuit that allows the stability and maximum input swing. Simulation result shows the enhanced phase margin and increased input swing with a proposed error amplifier.