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Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs
Ishihara, Shota,Xia, Zhengfan,Hariyama, Masanori,Kameyama, Michitaka The Institute of Electronics and Information Engin 2010 Journal of semiconductor technology and science Vol.10 No.3
This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.
Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs
Shota Ishihara,Zhengfan Xia,Masanori Hariyama,Michitaka Kameyama 대한전자공학회 2010 Journal of semiconductor technology and science Vol.10 No.3
This paper presents a fine-grain supplyvoltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltagecontrol scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 ㎚ CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.