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Hardware Platforms for Flash Memory/NVRAM Software Development
Eyee Hyun Nam,Ki Seok Choi,Jin-yong Choi,Hang Jun Min,Sang Lyul Min 한국정보과학회 2009 Journal of Computing Science and Engineering Vol.3 No.3
Flash memory is increasingly being used in a wide range of storage applications because of its low power consumption, low access latency, small form factor, and high shock resistance. However, the current platforms for flash memory software development do not meet the everincreasing requirements of flash memory applications. This paper presents three different hardware platforms for flash memory/NVRAM (non-volatile RAM) software development that overcome the limitations of the current platforms. The three platforms target different types of host system and provide various features that facilitate the development and verification of flash memory/NVRAM software. In this paper, we also demonstrate the usefulness of the three platforms by implementing three different types of storage system (one for each platform) based on them.
Hardware Platforms for Flash Memory/NVRAM Software Development
Nam, Eyee-Hyun,Choi, Ki-Seok,Choi, Jin-Yong,Min, Hang-Jun,Min, Sang-Lyul Korean Institute of Information Scientists and Eng 2009 Journal of Computing Science and Engineering Vol.3 No.3
Flash memory is increasingly being used in a wide range of storage applications because of its low power consumption, low access latency, small form factor, and high shock resistance. However, the current platforms for flash memory software development do not meet the ever-increasing requirements of flash memory applications. This paper presents three different hardware platforms for flash memory/NVRAM (non-volatile RAM) software development that overcome the limitations of the current platforms. The three platforms target different types of host system and provide various features that facilitate the development and verification of flash memory/NVRAM software. In this paper, we also demonstrate the usefulness of the three platforms by implementing three different types of storage system (one for each platform) based on them.
Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture
Yoon Jae Seong,Eyee Hyun Nam,Jin Hyuk Yoon,Hongseok Kim,Jin-yong Choi,Sookwan Lee,Young Hyun Bae,Jaejin Lee,Yookun Cho,Sang Lyul Min IEEE 2010 IEEE Transactions on Computers Vol.59 No.7
<P>Flash memory solid-state disks (SSDs) are replacing hard disk drives (HDDs) in mobile computing systems because of their lower power consumption, faster random access, and greater shock resistance. We describe Hydra, a high-performance flash memory SSD architecture that translates the parallelism inherent in multiple flash memory chips into improved performance, by means of both bus-level and chip-level interleaving. Hydra has a prioritized structure of memory controllers, consisting of a single high-priority foreground unit, to deal with read requests, and multiple background units, all capable of autonomous execution of sequences of high-level flash memory operations. Hydra also employs an aggressive write buffering mechanism based on block mapping to ensure that multiple flash memory chips are used effectively, and also to expedite the processing of write requests. Performance evaluation of an FPGA implementation of the Hydra SSD architecture shows that its performance is more than 80 percent better than the best of the comparable HDDs and SSDs that we considered.</P>
P-BMS : A Bad Block Management Scheme in Parallelized Flash Memory Storage Devices
Kim, Hong Seok,Nam, Eyee Hyun,Yun, Ji Hyuck,Lee, Sheayun,Min, Sang Lyul Association for Computing Machinery 2017 ACM transactions on embedded computing systems Vol.16 No.s5
<P>Flash memory is used as a main data storage medium in increasingly large areas of applications, rapidly replacing hard disk drives because of its low power consumption, fast random access, and high shock resistance. Such flash-based storage devices generally incorporate multiple flash memory chips to meet the ever growing capacity demands. Using multiple chips in a single storage device, at the same time, opens an opportunity to boost the performance based on multi-unit parallelism. However, parallel execution of multiple flash operations introduces complications when bad blocks occur, which is unavoidable due to flash memory's physical characteristics. The situation gets even worse when bad block occurrences are accompanied by sudden power failures. We propose a bad block management scheme called P-BMS that can fully utilize flash-level parallelism, while guaranteeing provably correct block replacement. Experiments show that our P-BMS achieves a throughput that is more than 95% of the maximum bandwidth of the flash controller, even with bad block occurrences far heavier than in real flash memory.</P>
HIL : A Framework for Compositional FTL Development and Provably-Correct Crash Recovery
Choi, Jin-Yong,Nam, Eyee Hyun,Seong, Yoon Jae,Yoon, Jin Hyuk,Lee, Sookwan,Kim, Hong Seok,Park, Jeongsu,Woo, Yeong-Jae,Lee, Sheayun,Min, Sang Lyul Association for Computing Machinery 2018 ACM transactions on storage Vol.14 No.4
An Abstract Fault Model for NAND Flash Memory
Ji Hyuck Yun,Jin Hyuk Yoon,Eyee Hyun Nam,Sang Lyul Min IEEE 2012 IEEE embedded systems letters Vol.4 No.4
<P>We present an abstract fault model for NAND flash memory that describes precisely the effects of various faults during a flash operation. The abstract model is intended to be used to reason about fault-related correctness of key modules of flash memory management software such as a flash translation layer (FTL). We also introduce the concept of “SAO-compliance” to raise awareness about fault-related vulnerabilities of current flash memory management software and to promote much needed research to fix them.</P>