TRENDS AND PERSPECTIVES IN INTEGRATED CIRCUITS AND SYSTEMS

Courtois,Bernard 대한전자공학회 1995 ICVC : International Conference on VLSI and CAD Vol.4 No.1

Electronics is expected to become the largest branch of industry around the year 2000, representing 10% of the world GNP. CAD represents just a bit more than i% and semiconductors 7% of the electronics market but they enable the $600 billion electronic systems' market. CAD Companies are evolving quickly, often growing through mergers and having to advance the state of their tools quickly in response to rapidly changing market needs. Major companies are Cadence and Mentor Graphics. Synopsys is growing rapidly in the synthesis market. ViewLogic was recently growing rapidly in the area of CAD tools for the low-end market. Low-end CAD tools for PCs are becoming more powerful, and are becoming more competitive with high-end products for workstations. At the same time; producers of high-end CAD tools are exploring strategies which will retain their competitive position despite the growing use of lower-end tools. Architecture synthesis tools are becoming increasingly important and developments in this area still benefit from research on silicon compilation, research that has been ongoing since the early 1980s. CATHEDRAL and AMICAL are representative of tools in this area. VHDL has become established as an important standard, along with VERILOG. In general, CAD tools are moving towards higher levels of description, with today's keywords including $quot;high-level$quot; design, $quot;system$quot; design, and $quot;architectural$quot; design. Several small companies are providing software which bridges between EDA tools and system tools. A global objective is to develop CAD tools capable of handling both hardware and software simultaneously (co-design), by bridging CASE and EDA tools. Productivity and innovation must be addressed by the research CAD community. Today, improvements in design productivity do not match the improvements occurring in the semiconductor technology, with the result that larger design teams are necessary for the more complex designs which can be placed on a single IC. The needs for advances in CAD tools remains large, though today's needs are different from those occurring a few years ago. The cost of manufacturing may impose serious limits, perhaps more important than physical device limits, in the continuing progression toward ever more advanced semiconductor fabrication processes. In particular, reversing a long term trend, the cost per transistor may begin to increase in successive generations of the technology, leading to costs per IC which increase more rapidly than the increase in the performance of the IC. Even though shared be several semiconductor companies, the cost of developing and fabricating very large memories may become too great to allow overall profits from sales of these memory components. Approaches other than downscaling of devices may allow a continuation of the decrease in the size of a system with the next generation technologies. Such alternative approaches include multichip modules (MCMs) and 3D packaging. MCMs are expected to show rapid market growth in the years to come, and 3D packaging prototypes are emerging. Problems to be solved inlcude testing issues, particularly those related to the full testing (including burn-in) of unpackaged, bare die, seeking to provide $quot;know good die$quot; for mounting on MCMs or for stacking into 3D units. In the area of production testing, boundary scan has emerged as a standard. Current testing (in which power supply currents are monitored) has emerged as a useful approach, complementing voltage testing and providing coverage of faults not readily detected by verification of logic level signals (voltage testing). Built-in current sensors have been integrated directly within ICs, allowing localized current testing. Concurrent testing has been developed theoretically over the last 20 years, and the first commencia] products are on the way. The trend in CAD is toward designing from higher and higher levels of abstraction in order to handle the increasingly complex circuits, with consequences on design verification and production testing. Design verification using formal techniques are increasingly needed since the use of simulation as a verification tool is becoming less appropriate. However, research is still needed to apply these formal techniques to higher complexity circuits. Production level testing must also consider low level fault models, since the classes of faults which must be represented become increasingly related to low level transistor behavior as the speed of the ICs increase. The challenge for testing is to adequately model the very complex circuits being produced using low-level fault models. Lastly, the continuing decrease in dimensions of ICs and the development of packaging techniques make thermal issues more and more crucial [SZEKELY 95]. Among the trends impacting design tools are the increasing applications of BiCMOS and GaAs ICs, expected to comprise about 5% and 2%, respectively, of the market in 1995. While silicon CMOS becomes an even more dominant mainstream technology, silicon bipolar circuitry will become less important, becoming negligible around the year 2000. Due to downscaling of the semiconductor technologies and the need for low power consumption, the power supply voltage is decreasing from 5 V to 3.3 V as feature sizes decrease below 0.6 ㎛. New circuit design approaches will be needed to eliminate the decrease in speed caused by the lower voltage. 3D integration, providing multiple layers of monolithic circuitry, remains a long term perspective, while continuing increases in the number of metal layers is a short term focus. Finally, FPGAs are emerging as particularly important IC components for several applications markets. Finally, it might happen that the most important (r)evolution of microelectronics will be the move to microsystems. Those microsystems might go out from the research laboratories to industry, provided that foundries and multi-purpose CAD emerge. Europe is benefiting from the development of several infrastructures. Several new European conferences been started over the past few years, the most important one being ED&TC. In the area of education, EUROCHIP has been an effort in terms of services provided to European universities, mostly in those countries which did not develop national initiatives in the past. This program is now finished. Recent initiative, CHIPSHOP, provides assistance to SMEs in the development and application of microelectronics. The prospects for the European industry presently appear strong. Some experts believe that Europe has the potential to become the world leader in semiconductors as smarter circuits such as ASICs, flash memory, EPROM, and related ICs become the main semiconductor circuit function. Initiatives such as JESSI are providing support in this direction. France, in particular, has been a pioneer in developing infrastructures for education and research, and with initiatives such as GRENOBLE 2000 placing SGS-Thomson and PHILIPS in a strong competitive position. A full paper on the topics addressed here is available [COURTOIS 94-2].

Trends in Fabrication , Design and CAD-European Perspectives

Courtois, Benard 대한전자공학회 1993 ICVC : International Conference on VLSI and CAD Vol.3 No.1

This paper deals with trends in different facets of microelectronics today. On fabrication, it is noticed that costs of manufacturing are an issue and brat besides UGSI, packaging techniques like 3D or MCMs will probably become more and more used. On the design aspects, differents trends are noted like the move from 5V to 3V as power supply, the importance of analog and mixed-signal circuits, the growth of BICMOS and GaAs circuits use, FPGAs, etc... CAD is also addressed to stress that productivity and innovation are the issues to be stressed. One way to increase productivity is to move to higher levels of synthesis than logic, i. e. to make use of emerging architectural synthesis tools. Lastly, European perspectives are addressed, in Terms of infrastructures, industrial developments, etc...

Design of Self-Checking Integrated Circuits and Boards

Courtois, B.,Nicolaidis, M.,Lubaszewski, M. 대한전자공학회 1991 ICVC : International Conference on VLSI and CAD Vol.2 No.1

This paper focuses on the design of ASICs featuring testing capabilities. Those capabilities include self-checking properties necessary for on-line testing as well as BIST. The design of fail-safe ASICs is addressed, aiming at the control of critical systems like transportation systems, nuclear plants, etc... Several case studies are briefly presented. A scheme providing the unification of the off-line test and the concurrent error detection at the board level is also discussed. This strategy conforms with the IEEE boundary scan standard.

Modern Radiotracing Tools for the Development of Engines, Lubricants, and After Treatment Systems

Thierry Delvigne,Olivier Courtois,Jay E. Ha(하재은) 한국자동차공학회 2009 한국자동차공학회 부문종합 학술대회 Vol.2009 No.4

Modern I.C. engines have to comply with strict environmental regulations, including a significant reduction of fuel consumption and emissions. This implies improvement of the internal combustion (I.C.) process, reduction of frictions, development of complex after treatment systems, and a reduction of oil consumption. New technical challenges are also associated to fuel dilution problems in diesel and super-ethanol engines, or to wear problems due to fuel dilution and soot loading in the lubricant, clogging and poisoning of after treatment system. Therefore, researchers and engineers need new tools to better understand and solve those new problems. In this paper, we describe the latest technologies available for engine and lubricant testing. The paper focuses on radionuclide techniques that are now increasingly used in Europe for realtime monitoring of engine wear, oil consumption, oil aeration, fuel dilution, and poisoning/clogging of after treatment systems. These technologies offer very high sensitivities and allow reducing significantly test durations. The paper presents the latest developments of radiotracer techniques applied to the development of engines, lubricants, and after treatment systems.

ROAD NOISE REDUCTION OF A SPORT UTILITY VEHICLE VIA PANEL SHAPE AND DAMPER OPTIMIZATION ON THE FLOOR USING GENETIC ALGORITHM

유지우,Francesca Ronzio,Theophane Courtois 한국자동차공학회 2019 International journal of automotive technology Vol.20 No.5

Road noise is always a major concern in automotive industries. The contribution of the floor of a automotive vehicle to road noise is large because of its large area and close location to chassis in terms of structure-borne noise. Therefore, the panel shape and damper of the floor should be carefully designed, which are effective on medium frequency region of the road noise. Because there are so many design options on the floor panels that experience high modal density and short wavelength at medium frequencies, traditional mode-decoupling approaches are no longer efficient. This study shows that a proposed optimization process based on a finite element model and a genetic algorithm is successful to reduce road noise at medium frequencies. Some background theories about the genetic algorithm and acoustic radiation efficiency in the frame of vibro-acoustics are explained to understand the optimization process. Vehicle performance evaluation and experimental study are given to validate this study. Finally, this verified process is applied to a sport utility vehicle (SUV) under development, whose road noise reduction is shown to be successful.

A New Algorithm for the Allocation of Functional Units and Connections onto Multiplexed Data Paths

park, In Hag,Brien, Kevin O`,Jerraya, Ahmed Amine,Courtois, Bernard 대한전자공학회 1991 ICVC : International Conference on VLSI and CAD Vol.2 No.1

This paper describes a new algorithm that allocates both functional unity (FUs), stored in an external user defined library, and connections. Our algorithm can generate several different structures by trading-off the costs of FUs and connections. This characteristic helps find a solution best fit to target architecture, because different target architectures demand different trade-offs. This algorithm is implemented in our data path synthesis system, called AMICAL, which facilitates the automatic, interactive or manual generation of microprocessor type data paths. The results obtained by this algorithm compare favorably with similar methods in the literature.

GLOBULAR CLUSTER POPULATIONS: RESULTS INCLUDING S⁴G LATE-TYPE GALAXIES

Zaritsky, Dennis,McCabe, Kelsey,Aravena, Manuel,Athanassoula, E.,Bosma, Albert,Comeró,n, Sé,bastien,Courtois, Helene M.,Elmegreen, Bruce G.,Elmegreen, Debra M.,Erroz-Ferrer, Santiago,Gadot American Astronomical Society 2016 The Astrophysical journal Vol.818 No.1

<P>Using 3.6 and 4.5 mu m images of 73 late-type, edge-on galaxies from the S(4)G survey, we compare the richness of the globular cluster populations of these galaxies to those of early-type galaxies that we measured previously. In general, the galaxies presented here fill in the distribution for galaxies with lower stellar mass, M-*, specifically log(M-*/M-circle dot) < 10, overlap the results for early-type galaxies of similar masses, and, by doing so, strengthen the case for a dependence of the number of globular clusters per 10(9)M(circle dot) of galaxy stellar mass, T-N, on M-*. For 8.5 < log(M-*/M-circle dot) < 10.5 we find the relationship can be satisfactorily described as T-N = (M-*/10(6.7))(-0.56) M-* is expressed in solar masses. The functional form of the relationship is only weakly constrained, and extrapolation outside this range is not advised. Our late-type galaxies, in contrast to our early types, do not show the tendency for low-mass galaxies to split into two T-N families. Using these results and a galaxy stellar mass function from the literature, we calculate that, in a volume-limited, local universe sample, clusters are most likely to be found around fairly massive galaxies (M-* similar to 10(10.8)M(circle dot)) and present a fitting function for the volume number density of clusters as a function of parent-galaxy stellar mass. We find no correlation between T-N and large-scale environment, but we do find a tendency for galaxies of fixed M-* to have larger T-N if they have converted a larger proportion of their baryons into stars.</P>

Local Electrical Characterization of PVDF Textile Filament

Anthony Ferri,François Rault,Antonio Da Costa,Cédric Cochrane,Matthieu Boudriaux,Guillaume Lemort,Christine Campagne,Eric Devaux,Christian Courtois,Rachel Desfeux 한국섬유공학회 2019 Fibers and polymers Vol.20 No.7

The piezoelectric behavior of poly(vinylidene fluoride), PVDF, has been known for several decades and is clearlyrelated to its crystalline phases. Many works made on films or fibers have focused on the characterization of the phasetransitions during various PVDF processing and on its electromechanical activity by combining several techniques. Piezoforcemicroscopy (PFM) is an interesting tool to underline the crystalline forms and piezoelectricity efficiency of PVDF atthe local scale. However, this technique is little used on samples in the form of fibers and in this case, it is most oftennanofibers. In this work, two conventional PVDF textile filaments, with different weak draw ratio, are produced and analyzedby FTIR, XRD, and PFM. We demonstrate that the PFM analysis can be relevant for specimens presenting low signals duringother characterizations. Therefore, the local piezo-/ferroelectricity into the fiber is highlighted underlining the existence of thepolar phases of PVDF. Then, the effective piezoelectric coefficient d33 of PVDF fiber drawn with a ratio of 1.5 is estimated at12 pm/V.