VHDL 지원환경에서 상위수준합성을 위한 CDFG생성 시스템의 설계 및 구현

김충석 新羅大學校 1992 論文集 Vol.33 No.1

This paper is on VHDL(Very high speed integrated circuit Hardware Description Language) Support Environment. Focuses on this study are to design and implement the CDFG(Control and Data Flow Graph) generating system for High Level Synthesis. VHDL, was accepted as Standard Hardware Descrip-tion Language system for High Level Synthesis. VHDL, was accepted as Standard Hardware Descrip-tion Language by IEEE(Institute of Electrical and Electronics Engineers) is used as input language the CDFG generating system. CDFG, generated by this system, is used as an input to High Level Synthesi-zer. Since VHDL syntax is too massive, it can not allow all kinds of syntax, the effort was made to deal with the behaviral description syntax. So far, I am trying to allow the VHDL fullset and extend the system continuously. To implementation, C language is used on UNLX System.

VHDL을 利用한 하드웨어 設計 自動環境에서의 中間코드에 關한 硏究

金忠錫 新羅大學校 1991 論文集 Vol.31 No.1

In this study, the VHDL Analyzer of IEEE standard VHDL(VHSIC Hardware Description Language) was designed and implemented. It accepts VHDL source program and generates an intermediate code which is shared in many other environments such as CAD-environment, simulator, reverse-analyzer, design-library, etc.. To implement this, the IDL(Interface Description language) which provides us the convenient generation environment was used. The analyzer generates the graph type code as an external VHDL intermediate code for readability like DIANA(Descriptive Intermediate Attributed Notaion for Ada)

검색형 정보시스템의 클라이언트-서버 개발에 관한 연구

김충석 신라대학교 자연과학연구소 1997 自然科學論文集 Vol.3 No.-

In recently, many organ's LAN(Local Area Network) that connected Internet are about to receive a new lease on life and become the invaluable tool it was always meant to be. For many years the payoff for installing and maintaining an internal network has often been elusive. Propretary software and systems often got in the way of those tring to create a powerful communication system for organ's constituent family members. That is Intranet. Intranets are rapidly becoming accepted and used by all organs because they offer the opportunity to use all the advances in telecommunication and presentation being developed for the Internet, and because they prepare constituents to use the Internet. In this study, present new client-server model for develop Intranet application software. The presented model is going down the effort of Intranet software developers.

표준네트워크보안과 수송계층보안의 구현

김충석,임채호 新羅大學校 1992 論文集 Vol.34 No.1

Since the OSI Security Architecture has been introduced by ISO, it gas been one of the most hot issue among the OSI security standard, Secured Data Network System(SDNS). And since it seems the most reseasonable candidate of International Standard, in this paper, SDNS composed of SP2, SP3, SP4, message security protocol and key management protocol, is surveyed and studied. Epecially this paper shows how to implement Security Protocol at layer 4 (SP4) and suggests implementation model. And by this suggested model, several SP4 components like as data confidentiality, integrity checking, pad parameter and direction indicatior are implemented in order to implement SP4 into ISO TPO provided by ISODE-6.0.

하드웨어 設計環境에서의 CDFG 形態에 관한 硏究

金賢培,金忠錫,朴淳東,高炳吾 新羅大學校 1991 論文集 Vol.32 No.1

In this study, design CDFG format in hardware design environment. It is used for high level synthesis in hardware design environment and supported in VHDL(VHSIC(Very High Speed Integrated Circuit) Hardware Description Language) Design Environment. This CDFG supports most of characteristic in hardware description language, concurrency, sequence, hierarchy etc. It is designed in consideration of VHDL, C, PASCAL, HardwareC. First, design CDFG and describe description rule then represent example of translation and grammar for CDFG paser.

TUP 중간언어를 위한 반복적인 자료흐름 분석기 구현에 관한 연구

김충석,박순동,이강우 新羅大學校 1993 論文集 Vol.36 No.1

In this study, we designs and implements the iterative data flow analyzer. that operates TUP intermediate programming language. Which produces some informations those are used a number of applications including code optimizations and parallelizations. instruction schedulings. testings, debuggings, certifications. Also we surveys many problems about data flow analysis and applies iterative techniques to solve the problems. Therefore the structure and concept of developed analyzer are very clear and easy. The analyzer computes some static informations about each variable including live range. loop depth. number of def/use, and needness of load/store at entry or exit of basic blocks, etc. The informations are used many optimization phase. especially, register allocation phase, common subexpression elimination phase and loop optimazation. We implements the data flow analyzer as two modules. live range analysis module and variable analysis module. The live range analysis module finds use/def point of each variable to generate live range. And variable analysis module computes loop depth. number of use/def. needness of load/store about each variable. Therefore the optimizating comiler using above informations can translate source program to more improved code. so execution times of improved code are saved than unimproved code. But complie times are increased because the compiler calls the data flow module and optimization module. Unfortunately. we skip the aliasing analyzer which is very important to data flow analysis because that analysis the aliasing relation between variables. And the results can change the many computed information. So, in recent, we are developing the alias processes. And we wish to expand the analyzer which operates on programs with many files. Besides we want to introduce incremental techniques and apply the techniques to the analyzer.

인터네트 보안 게이트웨이 구현

김충석,임채호 新羅大學校 1994 論文集 Vol.37 No.1

Since Internet has been started with the connection to US Internet and NSFNET, Korea R&D newworks such as KREON et, HANA, KREN have been suffered in security breaches by dimestic hackers. They intrude another Internet hosts using "telnet", TCP/IP terminal access protocol. So in this paper, the method to protect their unauthorized acess is introduced and implemented in gateway system between public Internet and a certain Internet domain. Through this paper, designed "AacServ" system provides : -User Authentication : Check accessed user is vaild or not -Access Control : Check user'd source host & destination host id. is the pre-registered one or not -Functions for Manager : Resistration, edition, view, deletion of User MIB, logging AacServ activities, report of AacServ event... This system can be easily be installed at any site of Internet because its configuration is very simple, and the test result was successful. To expand this system's functions, it will be studied how to apply security services into another TCP/IP applications, like SMTP electronic mail, FTP, and etc.

VHDL의 파서 구현

元裕憲,金忠錫 弘益大學校 1989 弘大論叢 Vol.21 No.2

In this study, we designed and implemented an analyzer for IEEE standard VHDL. It is one of the five tools in the VHDL support environment. The VHDL analyzer generated from LALR(1) accepts VHDL text to check syntactic and semantic validities. It generates error messages for the source text and an intermediate expression for other VHDL tools. This intermediate expression is made from symbol table and AST. The symbol table contains the information about attributes of identifiers and AST represents the entire structure of the source text. The implementation of symbol table and AST was done by adding C programs to the input of syntactic analysis. The analyzer was implemented in C language with Lex and Yacc in the UNIX system.

VHDL 언어를 이용한 Analyzer의 설계 및 구현

하수철,김충석 大田大學校 1988 論文集 Vol.7 No.2

This paper designs and implements an analyzer in the environment to support VHDL(VHSIC Hardware Description Language) standardized by IEEE. The VHDL analyzer accepts the source text for syntactic and semantic validity aginst the language definition In so doing,it builds an intermediate representation of the source at the VHDL designs library, which forms the basis for later manipulation of VHDL designs by other utilities. The intermediate representation is presented in the form of a file which comtains the attributes for the identifiers in the source text. The implementation in this paper is written with C language using Lex and Yacc on the XENIX system.

CDFG로 부터 VHDL Subset 추출

김충석(Choung-seok Kim),이영식(Young-sik Lee),표창우(Chang-woo Pyo),원유헌(Yoo-hun Won) 한국정보과학회 1992 한국정보과학회 학술발표논문집 Vol.19 No.1

본 논문에서는 하드웨어 상위수준 합성을 위한 Control and Data Flow Graph 로 부터 VHDL Subset을 생성하는 시스템 설계 및 구현에 관한 논문으로서 지난해의 “VHDL 로부터 CDFG 생성” 연구의 계속된 연구이다. 지난해의 연구인 VHDL로 부터 생성된 CDFG는 CDFG Editor를 거쳐 상위수준 합성을 위해 사용될 수 있다. 이번 연구에서는 Editor를 거쳐 완성된 CDFG를 다시 VHDL로 변환 시켜 봄으로서 생성된 VHDL을 상용화 된 Simulation 도구에서 실행시켜 CDFG를 검증 및 활용할 수 있다. CDFG를 VHDL로 변환하기 위해 parser를 구성 하였으며 parsing된 결과로는 table 형태의 자료구조를 이용하여 VHDL을 생성하였다. 생성된 VHDL은 Structural, Bebavioral 또는 Mixed description 형태의 VHDL Subset 이다. 이러한 연구는 한국전자통신연구소의 지원하에 이루어 지고 있으며 여기서 정의된 CDFG 형태도 ETRI에서 정의된 형태를 사용한다.