Legal Crisis and New Technology in Civil Courts: Urgent Need of Adopting Online Dispute Resolution in India

Choung,Yonghwan,Kumari,Saloni 대동문화재단 2021 대동CT연구 Vol.1 No.1

Expeditious settlement of disputes is pre-requisite of free economy, especially in the commercial matters. But pendency and backlog of cases in Indian judiciary has ransacked the working and functioning of nation as a whole. The underprivileged and poor people are the worst victim of this issue. Courtroom Litigation is a lengthy and expensive affair. And the pendency prolongs the cases for years depriving Justice to the needy as well as paralysing the economic activity of the nation. If this issue is not addressed in the near future, it has potential to crash the Indian judicial system under the weight of arrears. The idea of this paper is not to dwell upon the problem. It aims to explore the solutions and optimum methods needed for a reformative measure. Access of justice is a basic human right guaranteed by the common law. The Indian legal system is under constant pressure and questions have been raised as how do they plan to continue the justice delivery system. Thus, there is a need to prioritise the issue of pendency and access to justice to all. Since, a major dependency now lies upon the online and digital mode, the productivity during pandemic and even for future, can be enhanced through improved infrastructure of the online mode of alternative dispute settlement. The pandemic has reshaped how pending cases and future cases will be adjudicated. In light of this, the paper aims to divert the attention towards Alternative Dispute Resolution (“ADR”) and specifically Online modes of Dispute resolution and evaluate the efficacy of Online Dispute Resolution (“ODR”) mechanisms.

The Human Relations Theory

Choung,Woo Il(鄭宇一) 국민대학교 법학연구소 1983 法政論叢 Vol.5 No.1

韓國의 經濟發展과 金融産業의 效率化 方案

林海正,黃廷虎 군산대학교 산업개발연구소 1987 産業開發硏究 Vol.6 No.-

제주도 낙농발전을 위한 조사연구 : 젖소 개량 프로그램 정립을 위한 연구 ; (6) New Zealand의 낙농현황과 국제협력 방안

정창조 제주대학교 농과대학 제주도축산문제연구소 1990 畜産論叢 Vol.5 No.1

바나나 부산물의 사료화에 관한 연구

정창조,이왕식 제주대학교 농과대학 제주도축산문제연구소 1989 畜産論叢 Vol.4 No.1

검색형 정보시스템의 클라이언트-서버 개발에 관한 연구

김충석 신라대학교 자연과학연구소 1997 自然科學論文集 Vol.3 No.-

In recently, many organ's LAN(Local Area Network) that connected Internet are about to receive a new lease on life and become the invaluable tool it was always meant to be. For many years the payoff for installing and maintaining an internal network has often been elusive. Propretary software and systems often got in the way of those tring to create a powerful communication system for organ's constituent family members. That is Intranet. Intranets are rapidly becoming accepted and used by all organs because they offer the opportunity to use all the advances in telecommunication and presentation being developed for the Internet, and because they prepare constituents to use the Internet. In this study, present new client-server model for develop Intranet application software. The presented model is going down the effort of Intranet software developers.

TUP 중간언어를 위한 반복적인 자료흐름 분석기 구현에 관한 연구

김충석,박순동,이강우 新羅大學校 1993 論文集 Vol.36 No.1

In this study, we designs and implements the iterative data flow analyzer. that operates TUP intermediate programming language. Which produces some informations those are used a number of applications including code optimizations and parallelizations. instruction schedulings. testings, debuggings, certifications. Also we surveys many problems about data flow analysis and applies iterative techniques to solve the problems. Therefore the structure and concept of developed analyzer are very clear and easy. The analyzer computes some static informations about each variable including live range. loop depth. number of def/use, and needness of load/store at entry or exit of basic blocks, etc. The informations are used many optimization phase. especially, register allocation phase, common subexpression elimination phase and loop optimazation. We implements the data flow analyzer as two modules. live range analysis module and variable analysis module. The live range analysis module finds use/def point of each variable to generate live range. And variable analysis module computes loop depth. number of use/def. needness of load/store about each variable. Therefore the optimizating comiler using above informations can translate source program to more improved code. so execution times of improved code are saved than unimproved code. But complie times are increased because the compiler calls the data flow module and optimization module. Unfortunately. we skip the aliasing analyzer which is very important to data flow analysis because that analysis the aliasing relation between variables. And the results can change the many computed information. So, in recent, we are developing the alias processes. And we wish to expand the analyzer which operates on programs with many files. Besides we want to introduce incremental techniques and apply the techniques to the analyzer.

표준네트워크보안과 수송계층보안의 구현

김충석,임채호 新羅大學校 1992 論文集 Vol.34 No.1

Since the OSI Security Architecture has been introduced by ISO, it gas been one of the most hot issue among the OSI security standard, Secured Data Network System(SDNS). And since it seems the most reseasonable candidate of International Standard, in this paper, SDNS composed of SP2, SP3, SP4, message security protocol and key management protocol, is surveyed and studied. Epecially this paper shows how to implement Security Protocol at layer 4 (SP4) and suggests implementation model. And by this suggested model, several SP4 components like as data confidentiality, integrity checking, pad parameter and direction indicatior are implemented in order to implement SP4 into ISO TPO provided by ISODE-6.0.

프랑스어 학습평가 개선을 위한 방안

강충권 한국프랑스어문교육학회 2000 프랑스어문교육 Vol.10 No.-

De nos jours, 《la globalisation》 et 《la compe´tivite´ internationale》 s'imposent dans tous les domaines en Core´ee. Mais il est e´vident que ces deux buts ne seront atteints qu'a` condition qu'il y ait compe´tivite´ au niveau de la performance dans l'usage des langues e´trange`res. Dans un contexte pareil, nous pre´conisons 《l'approche communicative》 autant dans l'e´valuation que dans l'enseignement du franc¸ais en Core´e. Il s'agit dore´navant de changer le principe et la me´thode d'e´valuation. Pour re´sumer notre e´tude, nous insisterons sur les points suivants: En premier lieu, nous proposons l'e´valuation positive contre l'e´valuation ne´gative qui est en pratique trop souvent dans l'enseignement actuel et qui se contente de relever les fautes commises par les apprenants. Nous pensons qu'il faudrait mieux conside´rer ces fatutes comme des accidents de performance linguistique et e´valuer le degre´ de ce que les apprenants ont acquis, c´est-a`-dire la compe´tence acquise a` exprimer ses ide´es. D'autre part, proposer aux apprenants des exercices ouverts et varie´s qui collent a` la re´alite´ de la situation linguistique, et qui permettront une e´valuation plus exacte et fiable. Les exercices tels que <marquer vrai/faux>, <choisir la bonne re´ponse>, <mettre un ou quelques mots entre parenthe`ses> qu'on peut trouver encore dans la majeure partie des manuels core´ens et me^me ceux qui sont publie´es en France, se re´ve`lent trop peu efficaces pour ame´liorer la compe´tence linguistique des apprenants qui exige automatisme, fluidite´ et enfin cre´ativite´. Enfin, il faudra substituer une e´valuation absolue a` l'e´valuation relative en cours. Celle-ci qui est exige´e en Core´e au baccalaure´at et aussi aux examens pour e´tudiants universitaires n'est qu'une hie´rarchisation sans rapport re´el a` juger la compe´tence de communication des apprenants et e´choue, par conse´quent, a` devenir un feed-back pour l'enseignement pre´sent. Il nous semble qu'il est temps de changer la me´thode d'e´valuation de fac¸on sinon imme´diate, au moins graduelle.

VHDL을 利用한 하드웨어 設計 自動環境에서의 中間코드에 關한 硏究

金忠錫 新羅大學校 1991 論文集 Vol.31 No.1

In this study, the VHDL Analyzer of IEEE standard VHDL(VHSIC Hardware Description Language) was designed and implemented. It accepts VHDL source program and generates an intermediate code which is shared in many other environments such as CAD-environment, simulator, reverse-analyzer, design-library, etc.. To implement this, the IDL(Interface Description language) which provides us the convenient generation environment was used. The analyzer generates the graph type code as an external VHDL intermediate code for readability like DIANA(Descriptive Intermediate Attributed Notaion for Ada)