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- 저자 : Chaujar, Rishu (검색결과 3 건)
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RAHUL PANDEY,Rishu Chaujar 한국물리학회 2016 Current Applied Physics Vol.16 No.12
Nanostructuring has been projected as an appropriate technique to make thin silicon an efficient absorber. Although nano-textured surfaces have shown an anti-reflective effect, their surface passivation properties are found to be generally worse compared to standard micro-textured surfaces. Here, a novel front surface design has been proposed and simulated to balance the photonic and electronic effects together. ZrO2 based texturing has been used along with SiC-based front surface passivation for the suppression of interface recombination and improvement of open-circuit voltage (VOC). The device under investigation shows record VOC of 662 mV in the sub-10 mm-thick rear contact silicon solar cell. The presence of ZrO2 and SiC significantly improves the optical as well as the electrical behavior of the device. The device exhibits external quantum efficiency (EQE) > 81% in the spectrum range of 320e720 nm wavelength spectrum with a maximum of 95.6% at wavelength 560 nm. These improvements lead to 15.7% efficient rear contact silicon solar cell, in the sub-10 mm-thick regime. In second approach power conversion efficiency (PCE) of 21.6% has been achieved, by introducing the same front surface design to a 300 mm thick device. All the simulations have been done using calibrated software program in ATLAS device simulation.
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Linearity-Distortion Analysis of GME-TRC MOSFET for High Performance and Wireless Applications
Malik, Priyanka,Gupta, R.S.,Chaujar, Rishu,Gupta, Mridula The Institute of Electronics and Information Engin 2011 Journal of semiconductor technology and science Vol.11 No.3
In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: $g_{m1}$, $g_{m2}$, $g_{m3}$, and figure-of-merit (FOM) metrics; $V_{IP2}$, $V_{IP3}$, IIP3 and 1-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth ($X_j$) or negative junction depth (NJD) have been examined for GME-TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.
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Linearity-Distortion Analysis of GME- TRC MOSFET for High Performance and Wireless Applications
Priyanka Malik,R.S. Gupta,Rishu Chaujar,Mridula Gupta 대한전자공학회 2011 Journal of semiconductor technology and science Vol.11 No.3
In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: gm1, gm2, gm3, and figure-of-merit (FOM) metrics; VIP2, VIP3, IIP3 and I-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth (Xj) or negative junction depth (NJD) have been examined for GME- TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.
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