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RF CMOS Integrated On-Chip Tunable Absorptive Bandstop Filter Using Q-Tunable Resonators
Byungguk Kim,Jangjoon Lee,Juseop Lee,Byunghoo Jung,Chappell, William J. IEEE 2013 IEEE transactions on electron devices Vol.60 No.5
<P>A new approach for protecting sensitive receivers through large attenuation and its realization on-chip is presented for the first time. This paper demonstrates the use of absorptive bandstop filters that gives anomalously deep notches for a given quality factor. This approach is used in a fabricated design example to isolate a sensitive wideband LNA from interference in 45-nm SOI complementary metaloxide-semiconductor (CMOS). For reconfigurable RF front-ends, a frequency-agile design is newly developed with Q tunable resonators because an absorptive bandstop filter must balance both intrinsic Q of the resonators and the resonant frequency of the filter. Therefore, the design requires variable resistors, variable capacitors, and intimate coupling of inductors of disparate values. The layout of overlapping inductors on closely spaced metal layers is required for proper absorptive properties. The size of one filter presented in this paper is 310 by 340 μm, making it the smallest absorptive bandstop filter demonstrated so far. Despite using small-size, on-chip low-Q resonators in the bandstop filter design, an attenuation level from 31 to 63 dB and a frequency tuning range from 2.9 to 4.3 GHz are achieved with potential to suppress potential interference or an image frequency signal.</P>
Lu, Julia Hsin-Lin,Inerowicz, M,Sanghoon Joo,Jong-Kee Kwon,Byunghoo Jung IEEE 2011 IEEE SENSORS JOURNAL Vol.11 No.5
<P>We present a low-power, low complexity, and wide-dynamic-range universal sensor readout circuit that converts the sensing capacitance or resistance changes to digital duty cycles based on pulsewidth modulation (PWM). The readout circuit utilizes a RC-controlled pulse generator and produces pulse signals whose duration width is proportional to the charging time. The circuit is comprised of complementary CMOS circuit that enables the proposed design to consume significantly less power compared with traditional designs. The proposed design is universal and can be configured according to the application requirements. The sensor interface chip is designed and fabricated in TSMC 0.13-μm CMOS technology. The proposed interface achieves 13-aF to 10.7-nF capacitance and 5-Ω to 11.5-MΩ resistance sensing ranges with 60- μW power consumption. The functionality of the full circuit, including circuit analysis, noise analysis and measurement results, has been demonstrated.</P>