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Choi, Pyungho,Baek, Dohyun,Heo, Sung,Choi, Byoungdeog Elsevier 2018 THIN SOLID FILMS - Vol.652 No.-
<P><B>Abstract</B></P> <P>Hafnium‑zirconium silicate (HfZr-silicate, (HfZrO<SUB>4</SUB>)<SUB>1−x</SUB>(SiO<SUB>2</SUB>)<SUB>x</SUB>) thin films were developed for advanced gate stack applications by incorporating Si atoms into virgin hafnium‑zirconium oxide (HfZrO<SUB>4</SUB>) via atomic-layer deposition, yielding films with varying Si content (x=0.10, 0.15, and 0.20). Electron conduction behavior was responsible for a reduction in the gate leakage current of HfZr-silicate compared to pure HfZrO<SUB>4</SUB> films and was clearly explained by a conduction-electron generation model. Furthermore, HfZr-silicate-based structures exhibited less charge trapping and featured improved interfacial stability when in contact with Si substrate compared to virgin HfZrO<SUB>4</SUB>, although they both experienced bias and thermal stress. These phenomena were associated with the formation of an interfacial layer (IL) between virgin HfZrO<SUB>4</SUB> and the Si substrate, while there was no IL for the HfZr-silicate. With regard to the electrical properties of the films with varying Si incorporation, film with 15% SiO<SUB>2</SUB> was recommended as a high dielectric constant candidate due to its superior electrical properties and outstanding durability.</P> <P><B>Highlights</B></P> <P> <UL> <LI> (HfZrO<SUB>4</SUB>)<SUB>1−x</SUB>(SiO<SUB>2</SUB>)<SUB>x</SUB> dielectric films were developed and characterized. </LI> <LI> Thermal stabilities were enhanced with incorporation of SiO<SUB>2</SUB>. </LI> <LI> A film with 15% SiO<SUB>2</SUB> was demonstrated to be a high dielectric constant candidate. </LI> </UL> </P>
Comparison of Electrical Properties and Thermal Degradation of RGB-Organic Light Emitting Diodes
Choi, Pyungho,Park, Hyunae,Kim, Hyunwoo,Kim, Sangsoo,Choi, Byoungdeog American Scientific Publishers 2016 Journal of Nanoscience and Nanotechnology Vol.16 No.10
<P>The electrical properties and thermal degradation of red (R), green (G), and blue (B) organic-light-emitting-diodes (OLEDs) were characterized using the current-voltage (I-V) method. We investigated the temperature-dependent electrical degradation by determining the ideality factor n, series resistance r(s), and barrier height phi(B). The turn-on voltage for the R-OLED drastically decreased as temperature increased, whereas the others gradually decreased. Among the three types of OLEDs tested, the R-OLED showed the lowest current values under forward bias conditions as well as a severe temperature-dependency beyond the quasi-neutral region (QNR). The temperature-dependent variations of n and rs were largest for the R-OLED compared with the G-and B-OLEDs. This means that the R-OLED is the most easily degraded under thermal stress compared with the G-and B-OLEDs.</P>
Choi, Pyungho,Kim, Hyunjin,Kim, Sangsub,Kim, Soonkon,Javadi, Reza,Park, Hyoungsun,Choi, Byoungdeog American Scientific Publishers 2016 Journal of nanoscience and nanotechnology Vol.16 No.5
<P>In this study, pulse frequency and reverse bias voltage is modified in charge pumping and advanced technique is presented to extract oxide trap profile in hot carrier stressed thin gate oxide metal oxide semiconductor field effect transistors (MOSFETs). Carrier trapping-detrapping in a gate oxide was analyzed after hot carrier stress and the relationship between trapping depth and frequency was investigated. Hot carrier induced interface traps appears in whole channel area but induced border traps mainly appears in above pinch-off region near drain and gradually decreases toward center of the channel. Thus, hot carrier stress causes interface trap generation in whole channel area while most border trap generation occurs in the drain region under the gate. Ultimately, modified charge pumping method was performed to get trap density distribution of hot carrier stressed MOSFET devices, and the trapping-detrapping mechanism is also analyzed.</P>
Fabrication and Characteristics of High Mobility InSnZnO Thin Film Transistors
Choi, Pyungho,Lee, Junki,Park, Hyoungsun,Baek, Dohyun,Lee, Jaehyeong,Yi, Junsin,Kim, Sangsoo,Choi, Byoungdeog American Scientific Publishers 2016 Journal of nanoscience and nanotechnology Vol.16 No.5
<P>In this paper, we describe the fabrication of thin film transistors (TFTs) with amorphous indium-tin-zinc-oxide (ITZO) as the active material. A transparent ITZO channel layer was formed under an optimized oxygen partial pressure (OPP (%) = O-2/(Ar + O-2)) and subsequent annealing process. The electrical properties exhibited by this device include field-effect mobility (mu(eff)), sub-threshold swing (SS), and on/off current ratio (I-ON/OFF) values of 28.97 cm(2)/V.s, 0.2 V/decade, and 2.64 x 10(7), respectively. The average transmittance values for each OPP condition in the visible range were greater than 80%. The positive gate bias stress resulted in a positive threshold voltage (V-th) shift in the transfer curves and degraded the parameters mu(eff) and SS. These phenomena originated from electron trapping from the ITZO channel layer into the oxide/ITZO interface trap sites.</P>
Choi Byoungdeog,Choi Pyungho,Kim Soonkon,Jeon Bohyeon,Lee Jongyoon,Jungmin Park 대한전기학회 2021 Journal of Electrical Engineering & Technology Vol.16 No.2
This study investigates the eff ect of the gate SiO 2 thickness (80, 100, and 130 nm) deposited by plasma enhanced chemical vapor deposition on the interface and reliability characteristics of low-temperature polycrystalline silicon thin fi lm transistors. Field eff ect mobility is signifi cantly degraded as the gate oxide thickness decreases. The border trap density (N bt ) extracted from capacitance–voltage hysteresis exhibits no trend with respect to the gate oxide thickness, indicating that fi eld eff ect mobility is not governed by N bt . The quantitative interface trap density (N it ) was obtained using a 3-terminal charge pumping method; results showed that N it decreased as the gate oxide thickness increased. However, it was observed that the threshold voltage (V th ) shift during negative bias temperature stress is worse in the thicker SiO 2 fi lm, which has a low N it . After activation annealing, the amount of hydrogen in the gate oxide increased as the thickness of the insulator was raised. This in turn caused a larger shift in V th . To validate this mechanism, the amount of hydrogen with respect to the device depth was analyzed via secondary ion mass spectroscopy. It has been found that the presence of more hydrogen concentration in the SiO 2 fi lm and the interface to the thicker SiO 2 results in more V th shifts under bias temperature stress.
Choi, Pyungho,Kim, Dongsoo,Kim, Sangsub,Kim, Hyunwoo,Choi, Byoungdeog American Scientific Publishers 2016 Journal of nanoscience and nanotechnology Vol.16 No.10
<P>In this study, we characterized the interface and oxide charge generation in p-MOSFETs under negative bias temperature stress (NBTS). Thin (2.5 nm) and thick (6 nm) gate oxide MOSFETs were utilized to induce direct and Fowler-Nordheim (FN) tunneling, respectively. The threshold voltage and subthreshold swing in the thick oxide MOSFET was more significantly affected by NBTS than that of the thin oxide MOSFETs. The direct-current current-voltage (DCIV) method was implemented to investigate changes in trapped charges at the SiO2/Si interface. The change in oxide charges in the SiO2 bulk was obtained from the midgap voltage shift. The interface and oxide charges are predominantly affected by FN tunneling with less impact from direct tunneling, because of not only the hole-induced impact ionization at the SiO2/Si interface, but also the larger number of broken hydrogen atoms from the Si-H bonds, which are induced by the high applied gate bias. We conclude that devices' electrical performance can be significantly degraded when the MOSFETs are predominantly affected by FN tunneling rather than by direct tunneling under NBTS.</P>