A Low-Voltage Low-Power Opamp-Less 8-bit 1-MS/s Pipelined ADC in 90-nm CMOS Technology

Abbasizadeh, Hamed,Rikan, Behnam Samadpoor,Lee, Dong-Soo,Hayder, Abbas Syed,Lee, Kang-Yoon The Institute of Electronics and Information Engin 2014 IEIE Transactions on Smart Processing & Computing Vol.3 No.6

This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7V and 0.5V, respectively. This low power ADC utilizes the capacitive charge pump technique combined with a source-follower and calibration to resolve the need for the opamp. The differential charge pump technique does not require any common mode feedback circuit. The entire structure of the ADC is based on fully dynamic circuits that enable the design of a very low power ADC. The ADC was designed to operate at 1MS/s in 90nm CMOS process, where simulated results using ADS2011 show the peak SNDR and SFDR of the ADC to be 47.8 dB (7.64 ENOB) and 59 dB respectively. The ADC consumes less than 1mW for all active dynamic and digital circuitries.

Highly accurate capacitor-free LDO with sub-1 V −120 dB PSRR bandgap voltage reference

Abbasizadeh, H.,Hayder, A.S.,Lee, K.Y. IET 2016 Electronics letters Vol.52 No.15

<P>A low dropout (LDO) voltage regulator operated at 5 V power supply, along with a bandgap reference (BGR) voltage circuit with high power-supply rejection ratio (PSRR) is introduced. In the suggested LDO circuit, a low-pass filter for creating a common gate to transmit supply voltage to the power transistor gate is used. During deployment of the RC filter, an artificial resistor with a value of infinity is utilised, which in addition to reduce the chip occupied area, improves the performance of the low-pass filter at frequencies close to DC, and thus improves the PSRR at these frequencies. In addition, the high PSRR of the circuit is mediated by a low-voltage current mode regulator at the heart of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage (V-reg) for BGR core and op-amp rather than the V-DD. These current mirrors reduce the impact of supply voltage variations. The circuit topology is discussed and simulation results are provided. The LDO is also stable without an output capacitor.</P>

A 12 bit 750 kS/s 0.13 mW Dual-sampling SAR ADC

Abbasizadeh, Hamed,Lee, Dong-Soo,Yoo, Sang-Sun,Kim, Joon-Tae,Lee, Kang-Yoon The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.6

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

Accurate Sub-1 V CMOS Bandgap Voltage Reference with PSRR of -118 dB

Abbasizadeh, Hamed,Cho, Sung-Hun,Yoo, Sang-Sun,Lee, Kang-Yoon The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.4

A low voltage high PSRR CMOS Bandgap circuit capable of generating a stable voltage of less than 1 V (0.8 V and 0.5 V) robust to Process, Voltage and Temperature (PVT) variations is proposed. The high PSRR of the circuit is guaranteed by a low-voltage current mode regulator at the central aspect of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage $V_{reg}$ for the BG core and Op-Amp rather than the VDD. These current mirrors reduce the impact of supply voltage variations. The proposed circuit is implemented in a $0.35{\mu}m$ CMOS technology. The BGR circuit occupies $0.024mm^2$ of the die area and consumes $200{\mu}W$ from a 5 V supply voltage at room temperature. Experimental results demonstrate that the PSRR of the voltage reference achieved -118 dB at frequencies up to 1 kHz and -55 dB at 1 MHz without additional circuits for the curvature compensation. A temperature coefficient of $60 ppm/^{\circ}C$ is obtained in the range of -40 to $120^{\circ}C$.

Ultradense 2-to-4 decoder in quantum-dot cellular automata technology based on MV32 gate

Abbasizadeh, Akram,Mosleh, Mohammad Electronics and Telecommunications Research Instit 2020 ETRI Journal Vol.42 No.6

Quantum-dot cellular automata (QCA) is an alternative complementary metal-oxide-semiconductor (CMOS) technology that is used to implement high-speed logical circuits at the atomic or molecular scale. In this study, an optimal 2-to-4 decoder in QCA is presented. The proposed QCA decoder is designed using a new formulation based on the MV32 gate. Notably, the MV32 gate has three inputs and two outputs, which is equivalent two 3-input majority gates, and operates based on cellular interactions. A multilayer design is suggested for the proposed decoder. Subsequently, a new and efficient 3-to-8 QCA decoder architecture is presented using the proposed 2-to-4 QCA decoder. The simulation results of the QCADesigner 2.0.3 software show that the proposed decoders perform well. Comparisons show that the proposed 2-to-4 QCA decoder is superior to the previously proposed ones in terms of cell count, occupied area, and delay.

Sorption of heavy metal ions from aqueous solution by a novel cast PVA/TiO2 nanohybrid adsorbent functionalized with amine groups

Saeed Abbasizadeh,Ali Reza Keshtkar,Mohammad Ali Mousavian 한국공업화학회 2014 Journal of Industrial and Engineering Chemistry Vol.20 No.4

Sorption of Cd(II), Ni(II) and U(VI) ions onto a novel cast PVA/TiO2/APTES nanohybrid adsorbent with variations in adsorbent dose, pH, contact time, initial metal concentration and temperature has been investigated. The adsorbent were characterized by SEM and FTIR analysis. BET surface area, pore diameter and pore volume of adsorbent were 35.98 m2 g-1, 3.08 nm and 0.059 cm3 g-1, respectively. The kinetic and equilibrium data were accurately described by the double-exponential and Freundlich models for all metals. The maximum sorption capacities were 49.0, 13.1 and 36.1 mg g-1 for Cd(II), Ni(II) and U(VI) ions with pH of 5.5, 5 and 4.5, respectively. Thermodynamic studies showed that the sorption process was favored at higher temperature. The adsorbent can be easily regenerated after 5 cycles of sorption–desorption.

A 12 bit 750 kS/s 0.13 mW Dual-sampling SAR ADC

Hamed Abbasizadeh,Dong-Soo Lee,Sang-Sun Yoo,Joon-Tae Kim,Kang-Yoon Lee 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.6

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in 0.18-μm CMOS technology and occupies 0.728 mm2. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

A Sub 1 V New Bandgap Reference Circuit with PSRR of -120dB

Hamed Abbasizadeh,Behnam Samadpoor Rikan,Dong-Soo Lee,Kang-Yoon Lee 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6

A Bandgap circuit capable of generating a reference voltage of less than 1V with high PSRR, low process, supply voltage and temperature sensitivity is proposed. High PSRR achieved by means of an improved current mode regulator which isolates the bandgap voltage from the variations and the noise of the power supply. The proposed circuit is implemented in a 0.35μm CMOS technology. The BGR circuit occupies 0.024 mm² of die area and consumes 90μW from a 5V supply voltage at room temperature. Experimental results demonstrate that the PSRR of the voltage reference has achieved - 120dB at frequencies up to 1kHz and -58dB@1MHz. A temperature coefficient of 60 ppm/°C is obtained in the range of -40°C to 120°C.

Accurate Sub-1 V CMOS Bandgap Voltage Reference with PSRR of -118 ㏈

Hamed Abbasizadeh,Sung-Hun Cho,Sang-Sun Yoo,Kang-Yoon Lee 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.4

A low voltage high PSRR CMOS Bandgap circuit capable of generating a stable voltage of less than 1 V (0.8 V and 0.5 V) robust to Process, Voltage and Temperature (PVT) variations is proposed. The high PSRR of the circuit is guaranteed by a low-voltage current mode regulator at the central aspect of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage V<SUP>reg</SUP> for the BG core and Op-Amp rather than the V<SUP>DD</SUP>. These current mirrors reduce the impact of supply voltage variations. The proposed circuit is implemented in a 0.35 ㎛ CMOS technology. The BGR circuit occupies 0.024 ㎟ of the die area and consumes 200 ㎼ from a 5 V supply voltage at room temperature. Experimental results demonstrate that the PSRR of the voltage reference achieved -118 ㏈ at frequencies up to 1 ㎑ and -55 ㏈ at 1 ㎒ without additional circuits for the curvature compensation. A temperature coefficient of 60 ppm/℃ is obtained in the range of -40 to 120℃.

An Inductive 2-D Position Detection IC With 99.8% Accuracy for Automotive EMR Gear Control System

Kim, SangYun,Abbasizadeh, Hamed,Ali, Imran,Kim, Hongjin,Cho, SungHun,Pu, YoungGun,Yoo, Sang-Sun,Lee, Minjae,Hwang, Keum Cheol,Yang, Youngoo,Lee, Kang-Yoon IEEE 2017 IEEE transactions on very large scale integration Vol.25 No.5

<P>In this paper, the analog front end (AFE) for an inductive position sensor in an automotive electromagnetic resonance gear control applications is presented. To improve the position detection accuracy, a coil driver with an automatic two-step impedance calibration is proposed which, despite the load variation, provides the desired driving capability by controlling the main driver size. Also, a time shared analog-todigital converter (ADC) is proposed to convert eight-phase signals while reducing the current consumption and area to 1/8 of the conventional structure. A relaxation oscillator with temperature compensation is proposed to generate a constant clock frequency in vehicle temperature conditions. This chip is fabricated using a 0.18-mu m CMOS process and the die area is 2 mm x 1.5 mm. The power consumption of the AFE is 23.1 mW from the supply voltage of 3.3 V to drive one transmitter (Tx) coil and eight receiver (Rx) coils. The measured position detection accuracy is greater than 99.8 %. The measurement of the Tx shows a driving capability higher than 35 mA with respect to the load change.</P>