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ALICE Collaboration,Aamodt, K.,Abelev, B.,Abrahantes Quintana, A.,Adamova, D.,Adare, A.M.,Aggarwal, M.M.,Aglieri Rinella, G.,Agocs, A.G.,Agostinelli, A.,Aguilar Salazar, S.,Ahammed, Z.,Ahmad, N.,Ahmad North-Holland Pub. Co 2012 Physics letters: B Vol.708 No.3
Angular correlations between unidentified charged trigger (t) and associated (a) particles are measured by the ALICE experiment in Pb-Pb collisions at s<SUB>NN</SUB>=2.76 TeV for transverse momenta 0.25<p<SUB>T</SUB><SUP>t,a</SUP><15 GeV/c, where p<SUB>T</SUB><SUP>t</SUP>>p<SUB>T</SUB><SUP>a</SUP>. The shapes of the pair correlation distributions are studied in a variety of collision centrality classes between 0 and 50% of the total hadronic cross section for particles in the pseudorapidity interval |η|<1.0. Distributions in relative azimuth Δφ=φ<SUP>t</SUP>-φ<SUP>a</SUP> are analyzed for |Δη|=|η<SUP>t</SUP>-η<SUP>a</SUP>|>0.8, and are referred to as ''long-range correlations''. Fourier components V<SUB>nΔ</SUB>≤cos(nΔφ)> are extracted from the long-range azimuthal correlation functions. If particle pairs are correlated to one another through their individual correlation to a common symmetry plane, then the pair anisotropy V<SUB>nΔ</SUB>(p<SUB>T</SUB><SUP>t</SUP>,p<SUB>T</SUB><SUP>a</SUP>) is fully described in terms of single-particle anisotropies v<SUB>n</SUB>(p<SUB>T</SUB>) as V<SUB>nΔ</SUB>(p<SUB>T</SUB><SUP>t</SUP>,p<SUB>T</SUB><SUP>a</SUP>)=v<SUB>n</SUB>(p<SUB>T</SUB><SUP>t</SUP>)v<SUB>n</SUB>(p<SUB>T</SUB><SUP>a</SUP>). This expectation is tested for 1≤n≤5 by applying a global fit of all V<SUB>nΔ</SUB>(p<SUB>T</SUB><SUP>t</SUP>,p<SUB>T</SUB><SUP>a</SUP>) to obtain the best values v<SUB>n</SUB>{GF}(p<SUB>T</SUB>). It is found that for 2≤n≤5, the fit agrees well with data up to p<SUB>T</SUB><SUP>a</SUP>~3-4 GeV/c, with a trend of increasing deviation as p<SUB>T</SUB><SUP>t</SUP> and p<SUB>T</SUB><SUP>a</SUP> are increased or as collisions become more peripheral. This suggests that no pair correlation harmonic can be described over the full 0.25<p<SUB>T</SUB><15 GeV/c range using a single v<SUB>n</SUB>(p<SUB>T</SUB>) curve; such a description is however approximately possible for 2≤n≤5 when p<SUB>T</SUB><SUP>a</SUP><4 GeV/c. For the n=1 harmonic, however, a single v<SUB>1</SUB>(p<SUB>T</SUB>) curve is not obtained even within the reduced range p<SUB>T</SUB><SUP>a</SUP><4 GeV/c.
Two-pion Bose-Einstein correlations in central Pb-Pb collisions at s<sub>NN</sub>=2.76 TeV
ALICE Collaboration,Aamodt, K.,Abrahantes Quintana, A.,Adamova, D.,Adare, A.M.,Aggarwal, M.M.,Aglieri Rinella, G.,Agocs, A.G.,Aguilar Salazar, S.,Ahammed, Z.,Ahmad, N.,Ahmad Masoodi, A.,Ahn, S.U.,Akin North-Holland Pub. Co 2011 Physics letters: B Vol.696 No.4
The first measurement of two-pion Bose-Einstein correlations in central Pb-Pb collisions at s<SUB>NN</SUB>=2.76 TeV at the Large Hadron Collider is presented. We observe a growing trend with energy now not only for the longitudinal and the outward but also for the sideward pion source radius. The pion homogeneity volume and the decoupling time are significantly larger than those measured at RHIC.
Designing on-chip networks for throughput accelerators
Bakhoda, Ali,Kim, John,Aamodt, Tor M. Association for Computing Machinery 2013 ACM transactions on architecture and code optimiza Vol.10 No.3
<P>As the number of cores and threads in throughput accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network design. This article explores throughput-effective Network-on-Chips (NoC) for future compute accelerators that employ Bulk-Synchronous Parallel (BSP) programming models such as CUDA and OpenCL. A hardware optimization is 'throughput effective' if it improves parallel application-level performance per unit chip area. We evaluate performance of future looking workloads using detailed closed-loop simulations modeling compute nodes, NoC, and the DRAM memory system. We start from a mesh design with bisection bandwidth balanced to off-chip demand. Accelerator workloads tend to demand high off-chip memory bandwidth which results in a many-to-few traffic pattern when coupled with expected technology constraints of slow growth in pins-per-chip. Leveraging these observations we reduce NoC area by proposing a 'checkerboard' NoC which alternates between conventional full routers and half routers with limited connectivity. Next, we show that increasing network terminal bandwidth at the nodes connected to DRAM controllers alleviates a significant fraction of the remaining imbalance resulting from the many-to-few traffic pattern. Furthermore, we propose a 'double checkerboard inverted' NoC organization which takes advantage of channel slicing to reduce area while maintaining the performance improvements of the aforementioned techniques. This organization also has a simpler routing mechanism and improves average application throughput per unit area by 24.3%.</P>