http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
장복현,한재덕,김용대,차영욱,조경록,조태원 ( Bog Hyun Jang,Jae Duc Han,Yong Dai Kim,Young Uk Cha,Kyung Rof Cho,Tae Won Cho ) 충북대학교 산업과학기술연구소 1995 산업과학기술연구 논문집 Vol.9 No.1
Abstract_Roman We implemented a graphic user interface(GUI) which sends and receives data between two pe- rsonal computers through RS-232C. The transmitted data are displayed at the determined loca- tion on the GUI of another computer. There can be many
장복현,조태원 충북대학교컴퓨터과학연구소 1996 컴퓨터과학연구 Vol.4 No.1
We made 4-stage pipeline architecture and can execute 19 instruction set. The 16-bit RISC Processor CPU block is divided into 5 blocks: ALU, Control, RAM, ROM and RF(register file) blocks. This model compiled and synthesized by the Compass System 1164 VHDL compiler, and simulated by Compass simulator after synthesis. Total gate count was 6,351.00 gate. Simulation results show that this model satisfies good RISC pipeline operations. This model can operate up to 20MHz clock frequency, however by adjusting synthesis factors the frequency can easily be increased. We created .adl(actel design library) file and executed Place and Route(P&R) with A14100A-PG257C FPGA chip. Device utilization is 78.2% in sequential and combinational modules using Actel-3 library.