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비휘발성 메모리의 인접 비트라인 간 간섭을 완화하기 위한 비트라인 프리차지 방법
이태윤(Taeyun Lee),정성욱(Seong-Ook Jung) 대한전자공학회 2022 대한전자공학회 학술대회 Vol.2022 No.11
In NAND flash memory, which is a representative non-volatile memory, the bit-line pitch has been reduced to increase the degree of integration. This results in increased coupling between adjacent bit-lines, which increases the bit-line pre-charge time. In this paper, we propose Minimum Bit-line Current Control (MBCC), a novel bit-line pre-charge scheme that shortens the bit-line pre-charge time. MBCC reduces the range over which bit-line voltages are formed to reduce the amount of bit-line voltage variation caused by coupling between adjacent bitlines. MBCC implemented with an addition of 0.015% die area and 3% read operation current improves bit-line pre-charge time by 70.4%.
비트라인 트래킹을 위한 replica 기술에 관한 연구
오세혁(Oh, Se-Hyeok),정한울(Jung, Han-wool),정성욱(Jung, Seong-Ook) 한국전기전자학회 2016 전기전자학회논문지 Vol.20 No.2
정적 램의 비트라인을 정밀하게 추적하는 감지증폭기의 enable 신호를 만들기 위해 replica bit-line 기술 (RBL)이 사용된다. 하지만, 공정으로 인한 문턱전압의 변화는 replica bit-line 회로에 흐르는 전류를 변화시키고 이는 감지증폭기의 enable 신호 생성 시간 (T<sub>SAE</sub>)을 변화시키며, 결과적으로는 읽기 동작을 불안정하게 한다. 본 논문에서는 conventional replica bit-line delay (RBL<sub>conv</sub> )구조 및 T<sub>SAE</sub>변화를 감소시킬 수 있는 개선 구조인 dual replica bit-line delay (DRBD)구조와 multi-stage dual replica bit-line delay(MDRBD)구조를 소개하고, 14nm FinFET 공정, 동작전압 0.6V에서 각 기술들에 대한 읽기 성공률이 6V를 만족하는 최대 on-cell 개수를 simulation을 통해 찾고 이때 각 구조에 대한 performance와 에너지를 비교했다. 그 결과, RBL<sub>conv</sub> 대비 DRBD와 MDRBD의 performance는 각각 24.4%와 48.3% 저하되고 에너지 소모는 각각 8%와 32.4% 감소된 것을 관찰하였다. Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, T<sub>SAE</sub>. The variation of T<sub>SAE</sub> makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay (RBL<sub>conv</sub>), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing T<sub>SAE</sub> variation are briefly introduced, and the maximum possible number of on-cell which can satisfy 6σ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than RBL<sub>conv</sub> and energy consumption is reduced which 8% and 32.4% than RBL<sub>conv</sub>.
Computing-In-Memory (CIM)를 위한 eDRAM 셀 분석
김도한(Do-Han Kim),정인준(In-Jun Jung),안홍근(Hong-Keun Ahn),정성욱(Seong-Ook Jung) 대한전자공학회 2021 대한전자공학회 학술대회 Vol.2021 No.6
In this paper, we conduct an analysis of five existing logic-compatible embedded DRAM (eDRAM) cells (1T1C, 3T conventional, 3T boost, 2T, and 2T1C cells) to develop a suitable cell for eDRAM compute-in-memory (CIM). We compare and analyze to select the best cell to implement eDRAM CIM and explain why and limitations. Afterwards, we are planning to conduct a study on the cell that solved the limitations of the selected cells.
차세대 메모리를 위한 병렬적 Double Error Correcting BCH 복호기 설계에 관한 연구
최사라(Sara Choi),나태희(Taehui Na),송병규(Byungkyu Song),김정필(Jung Pill Kim),강승혁(Seung H. Kang),정성욱(Seong-Ook Jung) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.6
As the technology node scales down aggressively, it is hard to guarantee the reliability of memory due to the high occurrence of soft errors. Therefore, ECC is generally adopted in the memory system to improve the reliability. Especially for emerging memories, such as ReRAM, PRAM, and STT-MRAM, they usally uses Double Error Correction (DEC) BCH code because this code has relatively low overhead of read latency and circuit complexity. To reduce more read latency, parallel BCH decoding altorihms are proposed recently. In this paper, two ways of implementation for parallel BCH decoding algorithm are compared in terms of delay, area and power.