http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
High-Speed I/O Circuit을 위한 새로운 구조의 나노급 LILVTSCR ESD 보호회로에 대한 연구
이조운(Jo-Woon Lee),육승범(Seung-Bum Yuk),손정만(Jung-Man Son),박미정(Mi-Jung Park),구용서(Young-Seo Koo) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
A novel latch-up immunity low voltage trigger silicon-controlled rectifier (LILVTSCR) for high -speed I/O circuit. The proposed LILVTSCR offers a reduced triggering voltage level as well as the enhanced ESD performance of the SCR devices. From the simulation results, the triggering voltage of the LILVTSCR is 2.8V~7.2V as the gate length of the LILVTSCR device is 0.5㎛~1.0㎛. And this structure reduces the latch-up phenomenon by using tum on/off character of N-channel and P-channel MOSFETs in SCR structure.
새로운 구조의 LDMOSFET 소자 설계 및 전기적 특성 연구
박미정(Mi-Jung Park),이조운(Jo-Woon Lee),이재현(Jae-Hyun Lee),육승범(Seung-Bum Yuk),구용서(Yong-Seo Koo) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
In this study, New structural LDMOSFET is proposed and It’s electric Characteristic is analysed Compared with the conventional LDMOSFET, the proposed LDMOSFET exhibits better trade-off relation between the on-resistance and breakdown capability. Novel device employs Double-Drain/twin pwell and two different Drift doping, based on RESURF(Reduced-SURface-Field) principle. Consquently, proposed device designed with stand breakdown voltage of 310V and the specific on-resistance of 80mΩㆍ㎠ through optimization between the breakdown voltage and the specific on resistance of device.
새로운 구조의 나노급 ESD 보호소자 설계 및 제작에 관한 연구
김귀동(Kim, Kui-Dong),이조운(Lee, Jo-Woon),박상조(Park, Sang-Jo),이윤식(Lee, Yoon-Sik),구용서(Koo, Yong-Seo) 한국전기전자학회 2005 전기전자학회논문지 Vol.9 No.2
본 연구에서는 보다 낮은 트리거 전압을 갖는 새로운 구조의 LVTSCR과 Triple-well SCR ESD 보호회로를 제안 및 설계하여 나노급 회로에 적용하고자 하였다. 제안된 LVTSCR은 약 9V, 약 7mA의 트리거 전압과 전류 및 약 7mA의 홀딩전압 특성을 가지며, 0.8KV(150mA/um) 정도의 ESD 감내 특성을 나타낸다. 한편 Triple-well SCR은 6V, 40mA의 트리거 전압을 가지며, substrate 및 gate 바이어스에 의해 트리거 전압이 4-5.5V 까지 감소하였다. This paper presents the new structural Low voltage LVTSCR and TWSCR ESD protection circuit. The proposed ESD protection circuit has lower triggering voltage than conventional circuits. And the LVTSCR has the triggering voltage of 9V, current of 7mA and can pass below 0.8KV (150mA/um). The triggering voltage of the Triple-well SCR measured to 6V and the current is 40mA. By the substrate and gate bias, the triggering voltage is lowered down to 4~5.5V.